hi3670-clock.h (11940B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree binding constants for HiSilicon Hi3670 SoC 4 * 5 * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. 6 * Copyright (c) 2018 Linaro Ltd. 7 */ 8 9#ifndef __DT_BINDINGS_CLOCK_HI3670_H 10#define __DT_BINDINGS_CLOCK_HI3670_H 11 12/* clk in stub clock */ 13#define HI3670_CLK_STUB_CLUSTER0 0 14#define HI3670_CLK_STUB_CLUSTER1 1 15#define HI3670_CLK_STUB_GPU 2 16#define HI3670_CLK_STUB_DDR 3 17#define HI3670_CLK_STUB_DDR_VOTE 4 18#define HI3670_CLK_STUB_DDR_LIMIT 5 19#define HI3670_CLK_STUB_NUM 6 20 21/* clk in crg clock */ 22#define HI3670_CLKIN_SYS 0 23#define HI3670_CLKIN_REF 1 24#define HI3670_CLK_FLL_SRC 2 25#define HI3670_CLK_PPLL0 3 26#define HI3670_CLK_PPLL1 4 27#define HI3670_CLK_PPLL2 5 28#define HI3670_CLK_PPLL3 6 29#define HI3670_CLK_PPLL4 7 30#define HI3670_CLK_PPLL6 8 31#define HI3670_CLK_PPLL7 9 32#define HI3670_CLK_PPLL_PCIE 10 33#define HI3670_CLK_PCIEPLL_REV 11 34#define HI3670_CLK_SCPLL 12 35#define HI3670_PCLK 13 36#define HI3670_CLK_UART0_DBG 14 37#define HI3670_CLK_UART6 15 38#define HI3670_OSC32K 16 39#define HI3670_OSC19M 17 40#define HI3670_CLK_480M 18 41#define HI3670_CLK_INVALID 19 42#define HI3670_CLK_DIV_SYSBUS 20 43#define HI3670_CLK_FACTOR_MMC 21 44#define HI3670_CLK_SD_SYS 22 45#define HI3670_CLK_SDIO_SYS 23 46#define HI3670_CLK_DIV_A53HPM 24 47#define HI3670_CLK_DIV_320M 25 48#define HI3670_PCLK_GATE_UART0 26 49#define HI3670_CLK_FACTOR_UART0 27 50#define HI3670_CLK_FACTOR_USB3PHY_PLL 28 51#define HI3670_CLK_GATE_ABB_USB 29 52#define HI3670_CLK_GATE_UFSPHY_REF 30 53#define HI3670_ICS_VOLT_HIGH 31 54#define HI3670_ICS_VOLT_MIDDLE 32 55#define HI3670_VENC_VOLT_HOLD 33 56#define HI3670_VDEC_VOLT_HOLD 34 57#define HI3670_EDC_VOLT_HOLD 35 58#define HI3670_CLK_ISP_SNCLK_FAC 36 59#define HI3670_CLK_FACTOR_RXDPHY 37 60#define HI3670_AUTODIV_SYSBUS 38 61#define HI3670_AUTODIV_EMMC0BUS 39 62#define HI3670_PCLK_ANDGT_MMC1_PCIE 40 63#define HI3670_CLK_GATE_VCODECBUS_GT 41 64#define HI3670_CLK_ANDGT_SD 42 65#define HI3670_CLK_SD_SYS_GT 43 66#define HI3670_CLK_ANDGT_SDIO 44 67#define HI3670_CLK_SDIO_SYS_GT 45 68#define HI3670_CLK_A53HPM_ANDGT 46 69#define HI3670_CLK_320M_PLL_GT 47 70#define HI3670_CLK_ANDGT_UARTH 48 71#define HI3670_CLK_ANDGT_UARTL 49 72#define HI3670_CLK_ANDGT_UART0 50 73#define HI3670_CLK_ANDGT_SPI 51 74#define HI3670_CLK_ANDGT_PCIEAXI 52 75#define HI3670_CLK_DIV_AO_ASP_GT 53 76#define HI3670_CLK_GATE_CSI_TRANS 54 77#define HI3670_CLK_GATE_DSI_TRANS 55 78#define HI3670_CLK_ANDGT_PTP 56 79#define HI3670_CLK_ANDGT_OUT0 57 80#define HI3670_CLK_ANDGT_OUT1 58 81#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 82#define HI3670_CLK_ANDGT_VDEC 60 83#define HI3670_CLK_ANDGT_VENC 61 84#define HI3670_CLK_ISP_SNCLK_ANGT 62 85#define HI3670_CLK_ANDGT_RXDPHY 63 86#define HI3670_CLK_ANDGT_ICS 64 87#define HI3670_AUTODIV_DMABUS 65 88#define HI3670_CLK_MUX_SYSBUS 66 89#define HI3670_CLK_MUX_VCODECBUS 67 90#define HI3670_CLK_MUX_SD_SYS 68 91#define HI3670_CLK_MUX_SD_PLL 69 92#define HI3670_CLK_MUX_SDIO_SYS 70 93#define HI3670_CLK_MUX_SDIO_PLL 71 94#define HI3670_CLK_MUX_A53HPM 72 95#define HI3670_CLK_MUX_320M 73 96#define HI3670_CLK_MUX_UARTH 74 97#define HI3670_CLK_MUX_UARTL 75 98#define HI3670_CLK_MUX_UART0 76 99#define HI3670_CLK_MUX_I2C 77 100#define HI3670_CLK_MUX_SPI 78 101#define HI3670_CLK_MUX_PCIEAXI 79 102#define HI3670_CLK_MUX_AO_ASP 80 103#define HI3670_CLK_MUX_VDEC 81 104#define HI3670_CLK_MUX_VENC 82 105#define HI3670_CLK_ISP_SNCLK_MUX0 83 106#define HI3670_CLK_ISP_SNCLK_MUX1 84 107#define HI3670_CLK_ISP_SNCLK_MUX2 85 108#define HI3670_CLK_MUX_RXDPHY_CFG 86 109#define HI3670_CLK_MUX_ICS 87 110#define HI3670_CLK_DIV_CFGBUS 88 111#define HI3670_CLK_DIV_MMC0BUS 89 112#define HI3670_CLK_DIV_MMC1BUS 90 113#define HI3670_PCLK_DIV_MMC1_PCIE 91 114#define HI3670_CLK_DIV_VCODECBUS 92 115#define HI3670_CLK_DIV_SD 93 116#define HI3670_CLK_DIV_SDIO 94 117#define HI3670_CLK_DIV_UARTH 95 118#define HI3670_CLK_DIV_UARTL 96 119#define HI3670_CLK_DIV_UART0 97 120#define HI3670_CLK_DIV_I2C 98 121#define HI3670_CLK_DIV_SPI 99 122#define HI3670_CLK_DIV_PCIEAXI 100 123#define HI3670_CLK_DIV_AO_ASP 101 124#define HI3670_CLK_DIV_CSI_TRANS 102 125#define HI3670_CLK_DIV_DSI_TRANS 103 126#define HI3670_CLK_DIV_PTP 104 127#define HI3670_CLK_DIV_CLKOUT0_PLL 105 128#define HI3670_CLK_DIV_CLKOUT1_PLL 106 129#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 130#define HI3670_CLK_DIV_VDEC 108 131#define HI3670_CLK_DIV_VENC 109 132#define HI3670_CLK_ISP_SNCLK_DIV0 110 133#define HI3670_CLK_ISP_SNCLK_DIV1 111 134#define HI3670_CLK_ISP_SNCLK_DIV2 112 135#define HI3670_CLK_DIV_ICS 113 136#define HI3670_PPLL1_EN_ACPU 114 137#define HI3670_PPLL2_EN_ACPU 115 138#define HI3670_PPLL3_EN_ACPU 116 139#define HI3670_PPLL1_GT_CPU 117 140#define HI3670_PPLL2_GT_CPU 118 141#define HI3670_PPLL3_GT_CPU 119 142#define HI3670_CLK_GATE_PPLL2_MEDIA 120 143#define HI3670_CLK_GATE_PPLL3_MEDIA 121 144#define HI3670_CLK_GATE_PPLL4_MEDIA 122 145#define HI3670_CLK_GATE_PPLL6_MEDIA 123 146#define HI3670_CLK_GATE_PPLL7_MEDIA 124 147#define HI3670_PCLK_GPIO0 125 148#define HI3670_PCLK_GPIO1 126 149#define HI3670_PCLK_GPIO2 127 150#define HI3670_PCLK_GPIO3 128 151#define HI3670_PCLK_GPIO4 129 152#define HI3670_PCLK_GPIO5 130 153#define HI3670_PCLK_GPIO6 131 154#define HI3670_PCLK_GPIO7 132 155#define HI3670_PCLK_GPIO8 133 156#define HI3670_PCLK_GPIO9 134 157#define HI3670_PCLK_GPIO10 135 158#define HI3670_PCLK_GPIO11 136 159#define HI3670_PCLK_GPIO12 137 160#define HI3670_PCLK_GPIO13 138 161#define HI3670_PCLK_GPIO14 139 162#define HI3670_PCLK_GPIO15 140 163#define HI3670_PCLK_GPIO16 141 164#define HI3670_PCLK_GPIO17 142 165#define HI3670_PCLK_GPIO20 143 166#define HI3670_PCLK_GPIO21 144 167#define HI3670_PCLK_GATE_DSI0 145 168#define HI3670_PCLK_GATE_DSI1 146 169#define HI3670_HCLK_GATE_USB3OTG 147 170#define HI3670_ACLK_GATE_USB3DVFS 148 171#define HI3670_HCLK_GATE_SDIO 149 172#define HI3670_PCLK_GATE_PCIE_SYS 150 173#define HI3670_PCLK_GATE_PCIE_PHY 151 174#define HI3670_PCLK_GATE_MMC1_PCIE 152 175#define HI3670_PCLK_GATE_MMC0_IOC 153 176#define HI3670_PCLK_GATE_MMC1_IOC 154 177#define HI3670_CLK_GATE_DMAC 155 178#define HI3670_CLK_GATE_VCODECBUS2DDR 156 179#define HI3670_CLK_CCI400_BYPASS 157 180#define HI3670_CLK_GATE_CCI400 158 181#define HI3670_CLK_GATE_SD 159 182#define HI3670_HCLK_GATE_SD 160 183#define HI3670_CLK_GATE_SDIO 161 184#define HI3670_CLK_GATE_A57HPM 162 185#define HI3670_CLK_GATE_A53HPM 163 186#define HI3670_CLK_GATE_PA_A53 164 187#define HI3670_CLK_GATE_PA_A57 165 188#define HI3670_CLK_GATE_PA_G3D 166 189#define HI3670_CLK_GATE_GPUHPM 167 190#define HI3670_CLK_GATE_PERIHPM 168 191#define HI3670_CLK_GATE_AOHPM 169 192#define HI3670_CLK_GATE_UART1 170 193#define HI3670_CLK_GATE_UART4 171 194#define HI3670_PCLK_GATE_UART1 172 195#define HI3670_PCLK_GATE_UART4 173 196#define HI3670_CLK_GATE_UART2 174 197#define HI3670_CLK_GATE_UART5 175 198#define HI3670_PCLK_GATE_UART2 176 199#define HI3670_PCLK_GATE_UART5 177 200#define HI3670_CLK_GATE_UART0 178 201#define HI3670_CLK_GATE_I2C3 179 202#define HI3670_CLK_GATE_I2C4 180 203#define HI3670_CLK_GATE_I2C7 181 204#define HI3670_PCLK_GATE_I2C3 182 205#define HI3670_PCLK_GATE_I2C4 183 206#define HI3670_PCLK_GATE_I2C7 184 207#define HI3670_CLK_GATE_SPI1 185 208#define HI3670_CLK_GATE_SPI4 186 209#define HI3670_PCLK_GATE_SPI1 187 210#define HI3670_PCLK_GATE_SPI4 188 211#define HI3670_CLK_GATE_USB3OTG_REF 189 212#define HI3670_CLK_GATE_USB2PHY_REF 190 213#define HI3670_CLK_GATE_PCIEAUX 191 214#define HI3670_ACLK_GATE_PCIE 192 215#define HI3670_CLK_GATE_MMC1_PCIEAXI 193 216#define HI3670_CLK_GATE_PCIEPHY_REF 194 217#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 218#define HI3670_CLK_GATE_PCIEIO 196 219#define HI3670_CLK_GATE_PCIE_HP 197 220#define HI3670_CLK_GATE_AO_ASP 198 221#define HI3670_PCLK_GATE_PCTRL 199 222#define HI3670_CLK_CSI_TRANS_GT 200 223#define HI3670_CLK_DSI_TRANS_GT 201 224#define HI3670_CLK_GATE_PWM 202 225#define HI3670_ABB_AUDIO_EN0 203 226#define HI3670_ABB_AUDIO_EN1 204 227#define HI3670_ABB_AUDIO_GT_EN0 205 228#define HI3670_ABB_AUDIO_GT_EN1 206 229#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 230#define HI3670_PERI_VOLT_HOLD 208 231#define HI3670_PERI_VOLT_MIDDLE 209 232#define HI3670_CLK_GATE_ISP_SNCLK0 210 233#define HI3670_CLK_GATE_ISP_SNCLK1 211 234#define HI3670_CLK_GATE_ISP_SNCLK2 212 235#define HI3670_CLK_GATE_RXDPHY0_CFG 213 236#define HI3670_CLK_GATE_RXDPHY1_CFG 214 237#define HI3670_CLK_GATE_RXDPHY2_CFG 215 238#define HI3670_CLK_GATE_TXDPHY0_CFG 216 239#define HI3670_CLK_GATE_TXDPHY0_REF 217 240#define HI3670_CLK_GATE_TXDPHY1_CFG 218 241#define HI3670_CLK_GATE_TXDPHY1_REF 219 242#define HI3670_CLK_GATE_MEDIA_TCXO 220 243 244/* clk in sctrl */ 245#define HI3670_CLK_ANDGT_IOPERI 0 246#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 247#define HI3670_CLK_ANGT_ASP_SUBSYS 2 248#define HI3670_CLK_MUX_UFS_SUBSYS 3 249#define HI3670_CLK_MUX_CLKOUT0 4 250#define HI3670_CLK_MUX_CLKOUT1 5 251#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 252#define HI3670_CLK_MUX_ASP_PLL 7 253#define HI3670_CLK_DIV_AOBUS 8 254#define HI3670_CLK_DIV_UFS_SUBSYS 9 255#define HI3670_CLK_DIV_IOPERI 10 256#define HI3670_CLK_DIV_CLKOUT0_TCXO 11 257#define HI3670_CLK_DIV_CLKOUT1_TCXO 12 258#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 259#define HI3670_CLK_DIV_ASP_SUBSYS 14 260#define HI3670_PPLL0_EN_ACPU 15 261#define HI3670_PPLL0_GT_CPU 16 262#define HI3670_CLK_GATE_PPLL0_MEDIA 17 263#define HI3670_PCLK_GPIO18 18 264#define HI3670_PCLK_GPIO19 19 265#define HI3670_CLK_GATE_SPI 20 266#define HI3670_PCLK_GATE_SPI 21 267#define HI3670_CLK_GATE_UFS_SUBSYS 22 268#define HI3670_CLK_GATE_UFSIO_REF 23 269#define HI3670_PCLK_AO_GPIO0 24 270#define HI3670_PCLK_AO_GPIO1 25 271#define HI3670_PCLK_AO_GPIO2 26 272#define HI3670_PCLK_AO_GPIO3 27 273#define HI3670_PCLK_AO_GPIO4 28 274#define HI3670_PCLK_AO_GPIO5 29 275#define HI3670_PCLK_AO_GPIO6 30 276#define HI3670_CLK_GATE_OUT0 31 277#define HI3670_CLK_GATE_OUT1 32 278#define HI3670_PCLK_GATE_SYSCNT 33 279#define HI3670_CLK_GATE_SYSCNT 34 280#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 281#define HI3670_CLK_GATE_ASP_SUBSYS 36 282#define HI3670_CLK_GATE_ASP_TCXO 37 283#define HI3670_CLK_GATE_DP_AUDIO_PLL 38 284 285/* clk in pmuctrl */ 286#define HI3670_GATE_ABB_192 0 287 288/* clk in pctrl */ 289#define HI3670_GATE_UFS_TCXO_EN 0 290#define HI3670_GATE_USB_TCXO_EN 1 291 292/* clk in iomcu */ 293#define HI3670_CLK_GATE_I2C0 0 294#define HI3670_CLK_GATE_I2C1 1 295#define HI3670_CLK_GATE_I2C2 2 296#define HI3670_CLK_GATE_SPI0 3 297#define HI3670_CLK_GATE_SPI2 4 298#define HI3670_CLK_GATE_UART3 5 299#define HI3670_CLK_I2C0_GATE_IOMCU 6 300#define HI3670_CLK_I2C1_GATE_IOMCU 7 301#define HI3670_CLK_I2C2_GATE_IOMCU 8 302#define HI3670_CLK_SPI0_GATE_IOMCU 9 303#define HI3670_CLK_SPI2_GATE_IOMCU 10 304#define HI3670_CLK_UART3_GATE_IOMCU 11 305#define HI3670_CLK_GATE_PERI0_IOMCU 12 306 307/* clk in media1 */ 308#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 309#define HI3670_CLK_ANDGT_EDC0 1 310#define HI3670_CLK_ANDGT_LDI0 2 311#define HI3670_CLK_ANDGT_LDI1 3 312#define HI3670_CLK_MMBUF_PLL_ANDGT 4 313#define HI3670_PCLK_MMBUF_ANDGT 5 314#define HI3670_CLK_MUX_VIVOBUS 6 315#define HI3670_CLK_MUX_EDC0 7 316#define HI3670_CLK_MUX_LDI0 8 317#define HI3670_CLK_MUX_LDI1 9 318#define HI3670_CLK_SW_MMBUF 10 319#define HI3670_CLK_DIV_VIVOBUS 11 320#define HI3670_CLK_DIV_EDC0 12 321#define HI3670_CLK_DIV_LDI0 13 322#define HI3670_CLK_DIV_LDI1 14 323#define HI3670_ACLK_DIV_MMBUF 15 324#define HI3670_PCLK_DIV_MMBUF 16 325#define HI3670_ACLK_GATE_NOC_DSS 17 326#define HI3670_PCLK_GATE_NOC_DSS_CFG 18 327#define HI3670_PCLK_GATE_MMBUF_CFG 19 328#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 329#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 330#define HI3670_PCLK_GATE_DSS 22 331#define HI3670_ACLK_GATE_DSS 23 332#define HI3670_CLK_GATE_VIVOBUSFREQ 24 333#define HI3670_CLK_GATE_EDC0 25 334#define HI3670_CLK_GATE_LDI0 26 335#define HI3670_CLK_GATE_LDI1FREQ 27 336#define HI3670_CLK_GATE_BRG 28 337#define HI3670_ACLK_GATE_ASC 29 338#define HI3670_CLK_GATE_DSS_AXI_MM 30 339#define HI3670_CLK_GATE_MMBUF 31 340#define HI3670_PCLK_GATE_MMBUF 32 341#define HI3670_CLK_GATE_ATDIV_VIVO 33 342 343/* clk in media2 */ 344#define HI3670_CLK_GATE_VDECFREQ 0 345#define HI3670_CLK_GATE_VENCFREQ 1 346#define HI3670_CLK_GATE_ICSFREQ 2 347 348#endif /* __DT_BINDINGS_CLOCK_HI3670_H */