mt8195-clk.h (24960B)
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_MT8195_H 8#define _DT_BINDINGS_CLK_MT8195_H 9 10/* TOPCKGEN */ 11 12#define CLK_TOP_AXI 0 13#define CLK_TOP_SPM 1 14#define CLK_TOP_SCP 2 15#define CLK_TOP_BUS_AXIMEM 3 16#define CLK_TOP_VPP 4 17#define CLK_TOP_ETHDR 5 18#define CLK_TOP_IPE 6 19#define CLK_TOP_CAM 7 20#define CLK_TOP_CCU 8 21#define CLK_TOP_IMG 9 22#define CLK_TOP_CAMTM 10 23#define CLK_TOP_DSP 11 24#define CLK_TOP_DSP1 12 25#define CLK_TOP_DSP2 13 26#define CLK_TOP_DSP3 14 27#define CLK_TOP_DSP4 15 28#define CLK_TOP_DSP5 16 29#define CLK_TOP_DSP6 17 30#define CLK_TOP_DSP7 18 31#define CLK_TOP_IPU_IF 19 32#define CLK_TOP_MFG_CORE_TMP 20 33#define CLK_TOP_CAMTG 21 34#define CLK_TOP_CAMTG2 22 35#define CLK_TOP_CAMTG3 23 36#define CLK_TOP_CAMTG4 24 37#define CLK_TOP_CAMTG5 25 38#define CLK_TOP_UART 26 39#define CLK_TOP_SPI 27 40#define CLK_TOP_SPIS 28 41#define CLK_TOP_MSDC50_0_HCLK 29 42#define CLK_TOP_MSDC50_0 30 43#define CLK_TOP_MSDC30_1 31 44#define CLK_TOP_MSDC30_2 32 45#define CLK_TOP_INTDIR 33 46#define CLK_TOP_AUD_INTBUS 34 47#define CLK_TOP_AUDIO_H 35 48#define CLK_TOP_PWRAP_ULPOSC 36 49#define CLK_TOP_ATB 37 50#define CLK_TOP_PWRMCU 38 51#define CLK_TOP_DP 39 52#define CLK_TOP_EDP 40 53#define CLK_TOP_DPI 41 54#define CLK_TOP_DISP_PWM0 42 55#define CLK_TOP_DISP_PWM1 43 56#define CLK_TOP_USB_TOP 44 57#define CLK_TOP_SSUSB_XHCI 45 58#define CLK_TOP_USB_TOP_1P 46 59#define CLK_TOP_SSUSB_XHCI_1P 47 60#define CLK_TOP_USB_TOP_2P 48 61#define CLK_TOP_SSUSB_XHCI_2P 49 62#define CLK_TOP_USB_TOP_3P 50 63#define CLK_TOP_SSUSB_XHCI_3P 51 64#define CLK_TOP_I2C 52 65#define CLK_TOP_SENINF 53 66#define CLK_TOP_SENINF1 54 67#define CLK_TOP_SENINF2 55 68#define CLK_TOP_SENINF3 56 69#define CLK_TOP_GCPU 57 70#define CLK_TOP_DXCC 58 71#define CLK_TOP_DPMAIF_MAIN 59 72#define CLK_TOP_AES_UFSFDE 60 73#define CLK_TOP_UFS 61 74#define CLK_TOP_UFS_TICK1US 62 75#define CLK_TOP_UFS_MP_SAP_CFG 63 76#define CLK_TOP_VENC 64 77#define CLK_TOP_VDEC 65 78#define CLK_TOP_PWM 66 79#define CLK_TOP_MCUPM 67 80#define CLK_TOP_SPMI_P_MST 68 81#define CLK_TOP_SPMI_M_MST 69 82#define CLK_TOP_DVFSRC 70 83#define CLK_TOP_TL 71 84#define CLK_TOP_TL_P1 72 85#define CLK_TOP_AES_MSDCFDE 73 86#define CLK_TOP_DSI_OCC 74 87#define CLK_TOP_WPE_VPP 75 88#define CLK_TOP_HDCP 76 89#define CLK_TOP_HDCP_24M 77 90#define CLK_TOP_HD20_DACR_REF_CLK 78 91#define CLK_TOP_HD20_HDCP_CCLK 79 92#define CLK_TOP_HDMI_XTAL 80 93#define CLK_TOP_HDMI_APB 81 94#define CLK_TOP_SNPS_ETH_250M 82 95#define CLK_TOP_SNPS_ETH_62P4M_PTP 83 96#define CLK_TOP_SNPS_ETH_50M_RMII 84 97#define CLK_TOP_DGI_OUT 85 98#define CLK_TOP_NNA0 86 99#define CLK_TOP_NNA1 87 100#define CLK_TOP_ADSP 88 101#define CLK_TOP_ASM_H 89 102#define CLK_TOP_ASM_M 90 103#define CLK_TOP_ASM_L 91 104#define CLK_TOP_APLL1 92 105#define CLK_TOP_APLL2 93 106#define CLK_TOP_APLL3 94 107#define CLK_TOP_APLL4 95 108#define CLK_TOP_APLL5 96 109#define CLK_TOP_I2SO1_MCK 97 110#define CLK_TOP_I2SO2_MCK 98 111#define CLK_TOP_I2SI1_MCK 99 112#define CLK_TOP_I2SI2_MCK 100 113#define CLK_TOP_DPTX_MCK 101 114#define CLK_TOP_AUD_IEC_CLK 102 115#define CLK_TOP_A1SYS_HP 103 116#define CLK_TOP_A2SYS_HF 104 117#define CLK_TOP_A3SYS_HF 105 118#define CLK_TOP_A4SYS_HF 106 119#define CLK_TOP_SPINFI_BCLK 107 120#define CLK_TOP_NFI1X 108 121#define CLK_TOP_ECC 109 122#define CLK_TOP_AUDIO_LOCAL_BUS 110 123#define CLK_TOP_SPINOR 111 124#define CLK_TOP_DVIO_DGI_REF 112 125#define CLK_TOP_ULPOSC 113 126#define CLK_TOP_ULPOSC_CORE 114 127#define CLK_TOP_SRCK 115 128#define CLK_TOP_MFG_CK_FAST_REF 116 129#define CLK_TOP_CLK26M_D2 117 130#define CLK_TOP_CLK26M_D52 118 131#define CLK_TOP_IN_DGI 119 132#define CLK_TOP_IN_DGI_D2 120 133#define CLK_TOP_IN_DGI_D4 121 134#define CLK_TOP_IN_DGI_D6 122 135#define CLK_TOP_IN_DGI_D8 123 136#define CLK_TOP_MAINPLL_D3 124 137#define CLK_TOP_MAINPLL_D4 125 138#define CLK_TOP_MAINPLL_D4_D2 126 139#define CLK_TOP_MAINPLL_D4_D4 127 140#define CLK_TOP_MAINPLL_D4_D8 128 141#define CLK_TOP_MAINPLL_D5 129 142#define CLK_TOP_MAINPLL_D5_D2 130 143#define CLK_TOP_MAINPLL_D5_D4 131 144#define CLK_TOP_MAINPLL_D5_D8 132 145#define CLK_TOP_MAINPLL_D6 133 146#define CLK_TOP_MAINPLL_D6_D2 134 147#define CLK_TOP_MAINPLL_D6_D4 135 148#define CLK_TOP_MAINPLL_D6_D8 136 149#define CLK_TOP_MAINPLL_D7 137 150#define CLK_TOP_MAINPLL_D7_D2 138 151#define CLK_TOP_MAINPLL_D7_D4 139 152#define CLK_TOP_MAINPLL_D7_D8 140 153#define CLK_TOP_MAINPLL_D9 141 154#define CLK_TOP_UNIVPLL_D2 142 155#define CLK_TOP_UNIVPLL_D3 143 156#define CLK_TOP_UNIVPLL_D4 144 157#define CLK_TOP_UNIVPLL_D4_D2 145 158#define CLK_TOP_UNIVPLL_D4_D4 146 159#define CLK_TOP_UNIVPLL_D4_D8 147 160#define CLK_TOP_UNIVPLL_D5 148 161#define CLK_TOP_UNIVPLL_D5_D2 149 162#define CLK_TOP_UNIVPLL_D5_D4 150 163#define CLK_TOP_UNIVPLL_D5_D8 151 164#define CLK_TOP_UNIVPLL_D6 152 165#define CLK_TOP_UNIVPLL_D6_D2 153 166#define CLK_TOP_UNIVPLL_D6_D4 154 167#define CLK_TOP_UNIVPLL_D6_D8 155 168#define CLK_TOP_UNIVPLL_D6_D16 156 169#define CLK_TOP_UNIVPLL_D7 157 170#define CLK_TOP_UNIVPLL_192M 158 171#define CLK_TOP_UNIVPLL_192M_D4 159 172#define CLK_TOP_UNIVPLL_192M_D8 160 173#define CLK_TOP_UNIVPLL_192M_D16 161 174#define CLK_TOP_UNIVPLL_192M_D32 162 175#define CLK_TOP_APLL1_D3 163 176#define CLK_TOP_APLL1_D4 164 177#define CLK_TOP_APLL2_D3 165 178#define CLK_TOP_APLL2_D4 166 179#define CLK_TOP_APLL3_D4 167 180#define CLK_TOP_APLL4_D4 168 181#define CLK_TOP_APLL5_D4 169 182#define CLK_TOP_HDMIRX_APLL_D3 170 183#define CLK_TOP_HDMIRX_APLL_D4 171 184#define CLK_TOP_HDMIRX_APLL_D6 172 185#define CLK_TOP_MMPLL_D4 173 186#define CLK_TOP_MMPLL_D4_D2 174 187#define CLK_TOP_MMPLL_D4_D4 175 188#define CLK_TOP_MMPLL_D5 176 189#define CLK_TOP_MMPLL_D5_D2 177 190#define CLK_TOP_MMPLL_D5_D4 178 191#define CLK_TOP_MMPLL_D6 179 192#define CLK_TOP_MMPLL_D6_D2 180 193#define CLK_TOP_MMPLL_D7 181 194#define CLK_TOP_MMPLL_D9 182 195#define CLK_TOP_TVDPLL1_D2 183 196#define CLK_TOP_TVDPLL1_D4 184 197#define CLK_TOP_TVDPLL1_D8 185 198#define CLK_TOP_TVDPLL1_D16 186 199#define CLK_TOP_TVDPLL2_D2 187 200#define CLK_TOP_TVDPLL2_D4 188 201#define CLK_TOP_TVDPLL2_D8 189 202#define CLK_TOP_TVDPLL2_D16 190 203#define CLK_TOP_MSDCPLL_D2 191 204#define CLK_TOP_MSDCPLL_D4 192 205#define CLK_TOP_MSDCPLL_D16 193 206#define CLK_TOP_ETHPLL_D2 194 207#define CLK_TOP_ETHPLL_D8 195 208#define CLK_TOP_ETHPLL_D10 196 209#define CLK_TOP_DGIPLL_D2 197 210#define CLK_TOP_ULPOSC1 198 211#define CLK_TOP_ULPOSC1_D2 199 212#define CLK_TOP_ULPOSC1_D4 200 213#define CLK_TOP_ULPOSC1_D7 201 214#define CLK_TOP_ULPOSC1_D8 202 215#define CLK_TOP_ULPOSC1_D10 203 216#define CLK_TOP_ULPOSC1_D16 204 217#define CLK_TOP_ULPOSC2 205 218#define CLK_TOP_ADSPPLL_D2 206 219#define CLK_TOP_ADSPPLL_D4 207 220#define CLK_TOP_ADSPPLL_D8 208 221#define CLK_TOP_MEM_466M 209 222#define CLK_TOP_MPHONE_SLAVE_B 210 223#define CLK_TOP_PEXTP_PIPE 211 224#define CLK_TOP_UFS_RX_SYMBOL 212 225#define CLK_TOP_UFS_TX_SYMBOL 213 226#define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214 227#define CLK_TOP_UFS_RX_SYMBOL1 215 228#define CLK_TOP_FPC 216 229#define CLK_TOP_HDMIRX_P 217 230#define CLK_TOP_APLL12_DIV0 218 231#define CLK_TOP_APLL12_DIV1 219 232#define CLK_TOP_APLL12_DIV2 220 233#define CLK_TOP_APLL12_DIV3 221 234#define CLK_TOP_APLL12_DIV4 222 235#define CLK_TOP_APLL12_DIV9 223 236#define CLK_TOP_CFG_VPP0 224 237#define CLK_TOP_CFG_VPP1 225 238#define CLK_TOP_CFG_VDO0 226 239#define CLK_TOP_CFG_VDO1 227 240#define CLK_TOP_CFG_UNIPLL_SES 228 241#define CLK_TOP_CFG_26M_VPP0 229 242#define CLK_TOP_CFG_26M_VPP1 230 243#define CLK_TOP_CFG_26M_AUD 231 244#define CLK_TOP_CFG_AXI_EAST 232 245#define CLK_TOP_CFG_AXI_EAST_NORTH 233 246#define CLK_TOP_CFG_AXI_NORTH 234 247#define CLK_TOP_CFG_AXI_SOUTH 235 248#define CLK_TOP_CFG_EXT_TEST 236 249#define CLK_TOP_SSUSB_REF 237 250#define CLK_TOP_SSUSB_PHY_REF 238 251#define CLK_TOP_SSUSB_P1_REF 239 252#define CLK_TOP_SSUSB_PHY_P1_REF 240 253#define CLK_TOP_SSUSB_P2_REF 241 254#define CLK_TOP_SSUSB_PHY_P2_REF 242 255#define CLK_TOP_SSUSB_P3_REF 243 256#define CLK_TOP_SSUSB_PHY_P3_REF 244 257#define CLK_TOP_NR_CLK 245 258 259/* INFRACFG_AO */ 260 261#define CLK_INFRA_AO_PMIC_TMR 0 262#define CLK_INFRA_AO_PMIC_AP 1 263#define CLK_INFRA_AO_PMIC_MD 2 264#define CLK_INFRA_AO_PMIC_CONN 3 265#define CLK_INFRA_AO_SEJ 4 266#define CLK_INFRA_AO_APXGPT 5 267#define CLK_INFRA_AO_GCE 6 268#define CLK_INFRA_AO_GCE2 7 269#define CLK_INFRA_AO_THERM 8 270#define CLK_INFRA_AO_PWM_H 9 271#define CLK_INFRA_AO_PWM1 10 272#define CLK_INFRA_AO_PWM2 11 273#define CLK_INFRA_AO_PWM3 12 274#define CLK_INFRA_AO_PWM4 13 275#define CLK_INFRA_AO_PWM 14 276#define CLK_INFRA_AO_UART0 15 277#define CLK_INFRA_AO_UART1 16 278#define CLK_INFRA_AO_UART2 17 279#define CLK_INFRA_AO_UART3 18 280#define CLK_INFRA_AO_UART4 19 281#define CLK_INFRA_AO_GCE_26M 20 282#define CLK_INFRA_AO_CQ_DMA_FPC 21 283#define CLK_INFRA_AO_UART5 22 284#define CLK_INFRA_AO_HDMI_26M 23 285#define CLK_INFRA_AO_SPI0 24 286#define CLK_INFRA_AO_MSDC0 25 287#define CLK_INFRA_AO_MSDC1 26 288#define CLK_INFRA_AO_CG1_MSDC2 27 289#define CLK_INFRA_AO_MSDC0_SRC 28 290#define CLK_INFRA_AO_TRNG 29 291#define CLK_INFRA_AO_AUXADC 30 292#define CLK_INFRA_AO_CPUM 31 293#define CLK_INFRA_AO_HDMI_32K 32 294#define CLK_INFRA_AO_CEC_66M_H 33 295#define CLK_INFRA_AO_IRRX 34 296#define CLK_INFRA_AO_PCIE_TL_26M 35 297#define CLK_INFRA_AO_MSDC1_SRC 36 298#define CLK_INFRA_AO_CEC_66M_B 37 299#define CLK_INFRA_AO_PCIE_TL_96M 38 300#define CLK_INFRA_AO_DEVICE_APC 39 301#define CLK_INFRA_AO_ECC_66M_H 40 302#define CLK_INFRA_AO_DEBUGSYS 41 303#define CLK_INFRA_AO_AUDIO 42 304#define CLK_INFRA_AO_PCIE_TL_32K 43 305#define CLK_INFRA_AO_DBG_TRACE 44 306#define CLK_INFRA_AO_DRAMC_F26M 45 307#define CLK_INFRA_AO_IRTX 46 308#define CLK_INFRA_AO_SSUSB 47 309#define CLK_INFRA_AO_DISP_PWM 48 310#define CLK_INFRA_AO_CLDMA_B 49 311#define CLK_INFRA_AO_AUDIO_26M_B 50 312#define CLK_INFRA_AO_SPI1 51 313#define CLK_INFRA_AO_SPI2 52 314#define CLK_INFRA_AO_SPI3 53 315#define CLK_INFRA_AO_UNIPRO_SYS 54 316#define CLK_INFRA_AO_UNIPRO_TICK 55 317#define CLK_INFRA_AO_UFS_MP_SAP_B 56 318#define CLK_INFRA_AO_PWRMCU 57 319#define CLK_INFRA_AO_PWRMCU_BUS_H 58 320#define CLK_INFRA_AO_APDMA_B 59 321#define CLK_INFRA_AO_SPI4 60 322#define CLK_INFRA_AO_SPI5 61 323#define CLK_INFRA_AO_CQ_DMA 62 324#define CLK_INFRA_AO_AES_UFSFDE 63 325#define CLK_INFRA_AO_AES 64 326#define CLK_INFRA_AO_UFS_TICK 65 327#define CLK_INFRA_AO_SSUSB_XHCI 66 328#define CLK_INFRA_AO_MSDC0_SELF 67 329#define CLK_INFRA_AO_MSDC1_SELF 68 330#define CLK_INFRA_AO_MSDC2_SELF 69 331#define CLK_INFRA_AO_I2S_DMA 70 332#define CLK_INFRA_AO_AP_MSDC0 71 333#define CLK_INFRA_AO_MD_MSDC0 72 334#define CLK_INFRA_AO_CG3_MSDC2 73 335#define CLK_INFRA_AO_GCPU 74 336#define CLK_INFRA_AO_PCIE_PERI_26M 75 337#define CLK_INFRA_AO_GCPU_66M_B 76 338#define CLK_INFRA_AO_GCPU_133M_B 77 339#define CLK_INFRA_AO_DISP_PWM1 78 340#define CLK_INFRA_AO_FBIST2FPC 79 341#define CLK_INFRA_AO_DEVICE_APC_SYNC 80 342#define CLK_INFRA_AO_PCIE_P1_PERI_26M 81 343#define CLK_INFRA_AO_SPIS0 82 344#define CLK_INFRA_AO_SPIS1 83 345#define CLK_INFRA_AO_133M_M_PERI 84 346#define CLK_INFRA_AO_66M_M_PERI 85 347#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86 348#define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87 349#define CLK_INFRA_AO_PCIE_P1_TL_96M 88 350#define CLK_INFRA_AO_AES_MSDCFDE_0P 89 351#define CLK_INFRA_AO_UFS_TX_SYMBOL 90 352#define CLK_INFRA_AO_UFS_RX_SYMBOL 91 353#define CLK_INFRA_AO_UFS_RX_SYMBOL1 92 354#define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93 355#define CLK_INFRA_AO_NR_CLK 94 356 357/* APMIXEDSYS */ 358 359#define CLK_APMIXED_NNAPLL 0 360#define CLK_APMIXED_RESPLL 1 361#define CLK_APMIXED_ETHPLL 2 362#define CLK_APMIXED_MSDCPLL 3 363#define CLK_APMIXED_TVDPLL1 4 364#define CLK_APMIXED_TVDPLL2 5 365#define CLK_APMIXED_MMPLL 6 366#define CLK_APMIXED_MAINPLL 7 367#define CLK_APMIXED_VDECPLL 8 368#define CLK_APMIXED_IMGPLL 9 369#define CLK_APMIXED_UNIVPLL 10 370#define CLK_APMIXED_HDMIPLL1 11 371#define CLK_APMIXED_HDMIPLL2 12 372#define CLK_APMIXED_HDMIRX_APLL 13 373#define CLK_APMIXED_USB1PLL 14 374#define CLK_APMIXED_ADSPPLL 15 375#define CLK_APMIXED_APLL1 16 376#define CLK_APMIXED_APLL2 17 377#define CLK_APMIXED_APLL3 18 378#define CLK_APMIXED_APLL4 19 379#define CLK_APMIXED_APLL5 20 380#define CLK_APMIXED_MFGPLL 21 381#define CLK_APMIXED_DGIPLL 22 382#define CLK_APMIXED_PLL_SSUSB26M 23 383#define CLK_APMIXED_NR_CLK 24 384 385/* SCP_ADSP */ 386 387#define CLK_SCP_ADSP_AUDIODSP 0 388#define CLK_SCP_ADSP_NR_CLK 1 389 390/* PERICFG_AO */ 391 392#define CLK_PERI_AO_ETHERNET 0 393#define CLK_PERI_AO_ETHERNET_BUS 1 394#define CLK_PERI_AO_FLASHIF_BUS 2 395#define CLK_PERI_AO_FLASHIF_FLASH 3 396#define CLK_PERI_AO_SSUSB_1P_BUS 4 397#define CLK_PERI_AO_SSUSB_1P_XHCI 5 398#define CLK_PERI_AO_SSUSB_2P_BUS 6 399#define CLK_PERI_AO_SSUSB_2P_XHCI 7 400#define CLK_PERI_AO_SSUSB_3P_BUS 8 401#define CLK_PERI_AO_SSUSB_3P_XHCI 9 402#define CLK_PERI_AO_SPINFI 10 403#define CLK_PERI_AO_ETHERNET_MAC 11 404#define CLK_PERI_AO_NFI_H 12 405#define CLK_PERI_AO_FNFI1X 13 406#define CLK_PERI_AO_PCIE_P0_MEM 14 407#define CLK_PERI_AO_PCIE_P1_MEM 15 408#define CLK_PERI_AO_NR_CLK 16 409 410/* IMP_IIC_WRAP_S */ 411 412#define CLK_IMP_IIC_WRAP_S_I2C5 0 413#define CLK_IMP_IIC_WRAP_S_I2C6 1 414#define CLK_IMP_IIC_WRAP_S_I2C7 2 415#define CLK_IMP_IIC_WRAP_S_NR_CLK 3 416 417/* IMP_IIC_WRAP_W */ 418 419#define CLK_IMP_IIC_WRAP_W_I2C0 0 420#define CLK_IMP_IIC_WRAP_W_I2C1 1 421#define CLK_IMP_IIC_WRAP_W_I2C2 2 422#define CLK_IMP_IIC_WRAP_W_I2C3 3 423#define CLK_IMP_IIC_WRAP_W_I2C4 4 424#define CLK_IMP_IIC_WRAP_W_NR_CLK 5 425 426/* MFGCFG */ 427 428#define CLK_MFG_BG3D 0 429#define CLK_MFG_NR_CLK 1 430 431/* VPPSYS0 */ 432 433#define CLK_VPP0_MDP_FG 0 434#define CLK_VPP0_STITCH 1 435#define CLK_VPP0_PADDING 2 436#define CLK_VPP0_MDP_TCC 3 437#define CLK_VPP0_WARP0_ASYNC_TX 4 438#define CLK_VPP0_WARP1_ASYNC_TX 5 439#define CLK_VPP0_MUTEX 6 440#define CLK_VPP0_VPP02VPP1_RELAY 7 441#define CLK_VPP0_VPP12VPP0_ASYNC 8 442#define CLK_VPP0_MMSYSRAM_TOP 9 443#define CLK_VPP0_MDP_AAL 10 444#define CLK_VPP0_MDP_RSZ 11 445#define CLK_VPP0_SMI_COMMON 12 446#define CLK_VPP0_GALS_VDO0_LARB0 13 447#define CLK_VPP0_GALS_VDO0_LARB1 14 448#define CLK_VPP0_GALS_VENCSYS 15 449#define CLK_VPP0_GALS_VENCSYS_CORE1 16 450#define CLK_VPP0_GALS_INFRA 17 451#define CLK_VPP0_GALS_CAMSYS 18 452#define CLK_VPP0_GALS_VPP1_LARB5 19 453#define CLK_VPP0_GALS_VPP1_LARB6 20 454#define CLK_VPP0_SMI_REORDER 21 455#define CLK_VPP0_SMI_IOMMU 22 456#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23 457#define CLK_VPP0_MDP_RDMA 24 458#define CLK_VPP0_MDP_WROT 25 459#define CLK_VPP0_GALS_EMI0_EMI1 26 460#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27 461#define CLK_VPP0_SMI_RSI 28 462#define CLK_VPP0_SMI_COMMON_LARB4 29 463#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30 464#define CLK_VPP0_GALS_VPP1_WPE 31 465#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 466#define CLK_VPP0_FAKE_ENG 33 467#define CLK_VPP0_MDP_HDR 34 468#define CLK_VPP0_MDP_TDSHP 35 469#define CLK_VPP0_MDP_COLOR 36 470#define CLK_VPP0_MDP_OVL 37 471#define CLK_VPP0_WARP0_RELAY 38 472#define CLK_VPP0_WARP0_MDP_DL_ASYNC 39 473#define CLK_VPP0_WARP1_RELAY 40 474#define CLK_VPP0_WARP1_MDP_DL_ASYNC 41 475#define CLK_VPP0_NR_CLK 42 476 477/* WPESYS */ 478 479#define CLK_WPE_VPP0 0 480#define CLK_WPE_VPP1 1 481#define CLK_WPE_SMI_LARB7 2 482#define CLK_WPE_SMI_LARB8 3 483#define CLK_WPE_EVENT_TX 4 484#define CLK_WPE_SMI_LARB7_P 5 485#define CLK_WPE_SMI_LARB8_P 6 486#define CLK_WPE_NR_CLK 7 487 488/* WPESYS_VPP0 */ 489 490#define CLK_WPE_VPP0_VECI 0 491#define CLK_WPE_VPP0_VEC2I 1 492#define CLK_WPE_VPP0_VEC3I 2 493#define CLK_WPE_VPP0_WPEO 3 494#define CLK_WPE_VPP0_MSKO 4 495#define CLK_WPE_VPP0_VGEN 5 496#define CLK_WPE_VPP0_EXT 6 497#define CLK_WPE_VPP0_VFC 7 498#define CLK_WPE_VPP0_CACH0_TOP 8 499#define CLK_WPE_VPP0_CACH0_DMA 9 500#define CLK_WPE_VPP0_CACH1_TOP 10 501#define CLK_WPE_VPP0_CACH1_DMA 11 502#define CLK_WPE_VPP0_CACH2_TOP 12 503#define CLK_WPE_VPP0_CACH2_DMA 13 504#define CLK_WPE_VPP0_CACH3_TOP 14 505#define CLK_WPE_VPP0_CACH3_DMA 15 506#define CLK_WPE_VPP0_PSP 16 507#define CLK_WPE_VPP0_PSP2 17 508#define CLK_WPE_VPP0_SYNC 18 509#define CLK_WPE_VPP0_C24 19 510#define CLK_WPE_VPP0_MDP_CROP 20 511#define CLK_WPE_VPP0_ISP_CROP 21 512#define CLK_WPE_VPP0_TOP 22 513#define CLK_WPE_VPP0_NR_CLK 23 514 515/* WPESYS_VPP1 */ 516 517#define CLK_WPE_VPP1_VECI 0 518#define CLK_WPE_VPP1_VEC2I 1 519#define CLK_WPE_VPP1_VEC3I 2 520#define CLK_WPE_VPP1_WPEO 3 521#define CLK_WPE_VPP1_MSKO 4 522#define CLK_WPE_VPP1_VGEN 5 523#define CLK_WPE_VPP1_EXT 6 524#define CLK_WPE_VPP1_VFC 7 525#define CLK_WPE_VPP1_CACH0_TOP 8 526#define CLK_WPE_VPP1_CACH0_DMA 9 527#define CLK_WPE_VPP1_CACH1_TOP 10 528#define CLK_WPE_VPP1_CACH1_DMA 11 529#define CLK_WPE_VPP1_CACH2_TOP 12 530#define CLK_WPE_VPP1_CACH2_DMA 13 531#define CLK_WPE_VPP1_CACH3_TOP 14 532#define CLK_WPE_VPP1_CACH3_DMA 15 533#define CLK_WPE_VPP1_PSP 16 534#define CLK_WPE_VPP1_PSP2 17 535#define CLK_WPE_VPP1_SYNC 18 536#define CLK_WPE_VPP1_C24 19 537#define CLK_WPE_VPP1_MDP_CROP 20 538#define CLK_WPE_VPP1_ISP_CROP 21 539#define CLK_WPE_VPP1_TOP 22 540#define CLK_WPE_VPP1_NR_CLK 23 541 542/* VPPSYS1 */ 543 544#define CLK_VPP1_SVPP1_MDP_OVL 0 545#define CLK_VPP1_SVPP1_MDP_TCC 1 546#define CLK_VPP1_SVPP1_MDP_WROT 2 547#define CLK_VPP1_SVPP1_VPP_PAD 3 548#define CLK_VPP1_SVPP2_MDP_WROT 4 549#define CLK_VPP1_SVPP2_VPP_PAD 5 550#define CLK_VPP1_SVPP3_MDP_WROT 6 551#define CLK_VPP1_SVPP3_VPP_PAD 7 552#define CLK_VPP1_SVPP1_MDP_RDMA 8 553#define CLK_VPP1_SVPP1_MDP_FG 9 554#define CLK_VPP1_SVPP2_MDP_RDMA 10 555#define CLK_VPP1_SVPP2_MDP_FG 11 556#define CLK_VPP1_SVPP3_MDP_RDMA 12 557#define CLK_VPP1_SVPP3_MDP_FG 13 558#define CLK_VPP1_VPP_SPLIT 14 559#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15 560#define CLK_VPP1_SVPP1_MDP_TDSHP 16 561#define CLK_VPP1_SVPP1_MDP_COLOR 17 562#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18 563#define CLK_VPP1_SVPP2_VPP_MERGE 19 564#define CLK_VPP1_SVPP2_MDP_COLOR 20 565#define CLK_VPP1_VPPSYS1_GALS 21 566#define CLK_VPP1_SVPP3_VPP_MERGE 22 567#define CLK_VPP1_SVPP3_MDP_COLOR 23 568#define CLK_VPP1_VPPSYS1_LARB 24 569#define CLK_VPP1_SVPP1_MDP_RSZ 25 570#define CLK_VPP1_SVPP1_MDP_HDR 26 571#define CLK_VPP1_SVPP1_MDP_AAL 27 572#define CLK_VPP1_SVPP2_MDP_HDR 28 573#define CLK_VPP1_SVPP2_MDP_AAL 29 574#define CLK_VPP1_DL_ASYNC 30 575#define CLK_VPP1_LARB5_FAKE_ENG 31 576#define CLK_VPP1_SVPP3_MDP_HDR 32 577#define CLK_VPP1_SVPP3_MDP_AAL 33 578#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34 579#define CLK_VPP1_LARB6_FAKE_ENG 35 580#define CLK_VPP1_SVPP2_MDP_RSZ 36 581#define CLK_VPP1_SVPP3_MDP_RSZ 37 582#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38 583#define CLK_VPP1_DISP_MUTEX 39 584#define CLK_VPP1_SVPP2_MDP_TDSHP 40 585#define CLK_VPP1_SVPP3_MDP_TDSHP 41 586#define CLK_VPP1_VPP0_DL1_RELAY 42 587#define CLK_VPP1_HDMI_META 43 588#define CLK_VPP1_VPP_SPLIT_HDMI 44 589#define CLK_VPP1_DGI_IN 45 590#define CLK_VPP1_DGI_OUT 46 591#define CLK_VPP1_VPP_SPLIT_DGI 47 592#define CLK_VPP1_VPP0_DL_ASYNC 48 593#define CLK_VPP1_VPP0_DL_RELAY 49 594#define CLK_VPP1_VPP_SPLIT_26M 50 595#define CLK_VPP1_NR_CLK 51 596 597/* IMGSYS */ 598 599#define CLK_IMG_LARB9 0 600#define CLK_IMG_TRAW0 1 601#define CLK_IMG_TRAW1 2 602#define CLK_IMG_TRAW2 3 603#define CLK_IMG_TRAW3 4 604#define CLK_IMG_DIP0 5 605#define CLK_IMG_WPE0 6 606#define CLK_IMG_IPE 7 607#define CLK_IMG_DIP1 8 608#define CLK_IMG_WPE1 9 609#define CLK_IMG_GALS 10 610#define CLK_IMG_NR_CLK 11 611 612/* IMGSYS1_DIP_TOP */ 613 614#define CLK_IMG1_DIP_TOP_LARB10 0 615#define CLK_IMG1_DIP_TOP_DIP_TOP 1 616#define CLK_IMG1_DIP_TOP_NR_CLK 2 617 618/* IMGSYS1_DIP_NR */ 619 620#define CLK_IMG1_DIP_NR_RESERVE 0 621#define CLK_IMG1_DIP_NR_DIP_NR 1 622#define CLK_IMG1_DIP_NR_NR_CLK 2 623 624/* IMGSYS1_WPE */ 625 626#define CLK_IMG1_WPE_LARB11 0 627#define CLK_IMG1_WPE_WPE 1 628#define CLK_IMG1_WPE_NR_CLK 2 629 630/* IPESYS */ 631 632#define CLK_IPE_DPE 0 633#define CLK_IPE_FDVT 1 634#define CLK_IPE_ME 2 635#define CLK_IPE_TOP 3 636#define CLK_IPE_SMI_LARB12 4 637#define CLK_IPE_NR_CLK 5 638 639/* CAMSYS */ 640 641#define CLK_CAM_LARB13 0 642#define CLK_CAM_LARB14 1 643#define CLK_CAM_MAIN_CAM 2 644#define CLK_CAM_MAIN_CAMTG 3 645#define CLK_CAM_SENINF 4 646#define CLK_CAM_GCAMSVA 5 647#define CLK_CAM_GCAMSVB 6 648#define CLK_CAM_GCAMSVC 7 649#define CLK_CAM_SCAMSA 8 650#define CLK_CAM_SCAMSB 9 651#define CLK_CAM_CAMSV_TOP 10 652#define CLK_CAM_CAMSV_CQ 11 653#define CLK_CAM_ADL 12 654#define CLK_CAM_ASG 13 655#define CLK_CAM_PDA 14 656#define CLK_CAM_FAKE_ENG 15 657#define CLK_CAM_MAIN_MRAW0 16 658#define CLK_CAM_MAIN_MRAW1 17 659#define CLK_CAM_MAIN_MRAW2 18 660#define CLK_CAM_MAIN_MRAW3 19 661#define CLK_CAM_CAM2MM0_GALS 20 662#define CLK_CAM_CAM2MM1_GALS 21 663#define CLK_CAM_CAM2SYS_GALS 22 664#define CLK_CAM_NR_CLK 23 665 666/* CAMSYS_RAWA */ 667 668#define CLK_CAM_RAWA_LARBX 0 669#define CLK_CAM_RAWA_CAM 1 670#define CLK_CAM_RAWA_CAMTG 2 671#define CLK_CAM_RAWA_NR_CLK 3 672 673/* CAMSYS_YUVA */ 674 675#define CLK_CAM_YUVA_LARBX 0 676#define CLK_CAM_YUVA_CAM 1 677#define CLK_CAM_YUVA_CAMTG 2 678#define CLK_CAM_YUVA_NR_CLK 3 679 680/* CAMSYS_RAWB */ 681 682#define CLK_CAM_RAWB_LARBX 0 683#define CLK_CAM_RAWB_CAM 1 684#define CLK_CAM_RAWB_CAMTG 2 685#define CLK_CAM_RAWB_NR_CLK 3 686 687/* CAMSYS_YUVB */ 688 689#define CLK_CAM_YUVB_LARBX 0 690#define CLK_CAM_YUVB_CAM 1 691#define CLK_CAM_YUVB_CAMTG 2 692#define CLK_CAM_YUVB_NR_CLK 3 693 694/* CAMSYS_MRAW */ 695 696#define CLK_CAM_MRAW_LARBX 0 697#define CLK_CAM_MRAW_CAMTG 1 698#define CLK_CAM_MRAW_MRAW0 2 699#define CLK_CAM_MRAW_MRAW1 3 700#define CLK_CAM_MRAW_MRAW2 4 701#define CLK_CAM_MRAW_MRAW3 5 702#define CLK_CAM_MRAW_NR_CLK 6 703 704/* CCUSYS */ 705 706#define CLK_CCU_LARB18 0 707#define CLK_CCU_AHB 1 708#define CLK_CCU_CCU0 2 709#define CLK_CCU_CCU1 3 710#define CLK_CCU_NR_CLK 4 711 712/* VDECSYS_SOC */ 713 714#define CLK_VDEC_SOC_LARB1 0 715#define CLK_VDEC_SOC_LAT 1 716#define CLK_VDEC_SOC_VDEC 2 717#define CLK_VDEC_SOC_NR_CLK 3 718 719/* VDECSYS */ 720 721#define CLK_VDEC_LARB1 0 722#define CLK_VDEC_LAT 1 723#define CLK_VDEC_VDEC 2 724#define CLK_VDEC_NR_CLK 3 725 726/* VDECSYS_CORE1 */ 727 728#define CLK_VDEC_CORE1_LARB1 0 729#define CLK_VDEC_CORE1_LAT 1 730#define CLK_VDEC_CORE1_VDEC 2 731#define CLK_VDEC_CORE1_NR_CLK 3 732 733/* APUSYS_PLL */ 734 735#define CLK_APUSYS_PLL_APUPLL 0 736#define CLK_APUSYS_PLL_NPUPLL 1 737#define CLK_APUSYS_PLL_APUPLL1 2 738#define CLK_APUSYS_PLL_APUPLL2 3 739#define CLK_APUSYS_PLL_NR_CLK 4 740 741/* VENCSYS */ 742 743#define CLK_VENC_LARB 0 744#define CLK_VENC_VENC 1 745#define CLK_VENC_JPGENC 2 746#define CLK_VENC_JPGDEC 3 747#define CLK_VENC_JPGDEC_C1 4 748#define CLK_VENC_GALS 5 749#define CLK_VENC_NR_CLK 6 750 751/* VENCSYS_CORE1 */ 752 753#define CLK_VENC_CORE1_LARB 0 754#define CLK_VENC_CORE1_VENC 1 755#define CLK_VENC_CORE1_JPGENC 2 756#define CLK_VENC_CORE1_JPGDEC 3 757#define CLK_VENC_CORE1_JPGDEC_C1 4 758#define CLK_VENC_CORE1_GALS 5 759#define CLK_VENC_CORE1_NR_CLK 6 760 761/* VDOSYS0 */ 762 763#define CLK_VDO0_DISP_OVL0 0 764#define CLK_VDO0_DISP_COLOR0 1 765#define CLK_VDO0_DISP_COLOR1 2 766#define CLK_VDO0_DISP_CCORR0 3 767#define CLK_VDO0_DISP_CCORR1 4 768#define CLK_VDO0_DISP_AAL0 5 769#define CLK_VDO0_DISP_AAL1 6 770#define CLK_VDO0_DISP_GAMMA0 7 771#define CLK_VDO0_DISP_GAMMA1 8 772#define CLK_VDO0_DISP_DITHER0 9 773#define CLK_VDO0_DISP_DITHER1 10 774#define CLK_VDO0_DISP_OVL1 11 775#define CLK_VDO0_DISP_WDMA0 12 776#define CLK_VDO0_DISP_WDMA1 13 777#define CLK_VDO0_DISP_RDMA0 14 778#define CLK_VDO0_DISP_RDMA1 15 779#define CLK_VDO0_DSI0 16 780#define CLK_VDO0_DSI1 17 781#define CLK_VDO0_DSC_WRAP0 18 782#define CLK_VDO0_VPP_MERGE0 19 783#define CLK_VDO0_DP_INTF0 20 784#define CLK_VDO0_DISP_MUTEX0 21 785#define CLK_VDO0_DISP_IL_ROT0 22 786#define CLK_VDO0_APB_BUS 23 787#define CLK_VDO0_FAKE_ENG0 24 788#define CLK_VDO0_FAKE_ENG1 25 789#define CLK_VDO0_DL_ASYNC0 26 790#define CLK_VDO0_DL_ASYNC1 27 791#define CLK_VDO0_DL_ASYNC2 28 792#define CLK_VDO0_DL_ASYNC3 29 793#define CLK_VDO0_DL_ASYNC4 30 794#define CLK_VDO0_DISP_MONITOR0 31 795#define CLK_VDO0_DISP_MONITOR1 32 796#define CLK_VDO0_DISP_MONITOR2 33 797#define CLK_VDO0_DISP_MONITOR3 34 798#define CLK_VDO0_DISP_MONITOR4 35 799#define CLK_VDO0_SMI_GALS 36 800#define CLK_VDO0_SMI_COMMON 37 801#define CLK_VDO0_SMI_EMI 38 802#define CLK_VDO0_SMI_IOMMU 39 803#define CLK_VDO0_SMI_LARB 40 804#define CLK_VDO0_SMI_RSI 41 805#define CLK_VDO0_DSI0_DSI 42 806#define CLK_VDO0_DSI1_DSI 43 807#define CLK_VDO0_DP_INTF0_DP_INTF 44 808#define CLK_VDO0_NR_CLK 45 809 810/* VDOSYS1 */ 811 812#define CLK_VDO1_SMI_LARB2 0 813#define CLK_VDO1_SMI_LARB3 1 814#define CLK_VDO1_GALS 2 815#define CLK_VDO1_FAKE_ENG0 3 816#define CLK_VDO1_FAKE_ENG 4 817#define CLK_VDO1_MDP_RDMA0 5 818#define CLK_VDO1_MDP_RDMA1 6 819#define CLK_VDO1_MDP_RDMA2 7 820#define CLK_VDO1_MDP_RDMA3 8 821#define CLK_VDO1_VPP_MERGE0 9 822#define CLK_VDO1_VPP_MERGE1 10 823#define CLK_VDO1_VPP_MERGE2 11 824#define CLK_VDO1_VPP_MERGE3 12 825#define CLK_VDO1_VPP_MERGE4 13 826#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 827#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15 828#define CLK_VDO1_DISP_MUTEX 16 829#define CLK_VDO1_MDP_RDMA4 17 830#define CLK_VDO1_MDP_RDMA5 18 831#define CLK_VDO1_MDP_RDMA6 19 832#define CLK_VDO1_MDP_RDMA7 20 833#define CLK_VDO1_DP_INTF0_MM 21 834#define CLK_VDO1_DPI0_MM 22 835#define CLK_VDO1_DPI1_MM 23 836#define CLK_VDO1_DISP_MONITOR 24 837#define CLK_VDO1_MERGE0_DL_ASYNC 25 838#define CLK_VDO1_MERGE1_DL_ASYNC 26 839#define CLK_VDO1_MERGE2_DL_ASYNC 27 840#define CLK_VDO1_MERGE3_DL_ASYNC 28 841#define CLK_VDO1_MERGE4_DL_ASYNC 29 842#define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30 843#define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 844#define CLK_VDO1_HDR_VDO_FE0 32 845#define CLK_VDO1_HDR_GFX_FE0 33 846#define CLK_VDO1_HDR_VDO_BE 34 847#define CLK_VDO1_HDR_VDO_FE1 35 848#define CLK_VDO1_HDR_GFX_FE1 36 849#define CLK_VDO1_DISP_MIXER 37 850#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38 851#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39 852#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40 853#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41 854#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42 855#define CLK_VDO1_DPI0 43 856#define CLK_VDO1_DISP_MONITOR_DPI0 44 857#define CLK_VDO1_DPI1 45 858#define CLK_VDO1_DISP_MONITOR_DPI1 46 859#define CLK_VDO1_DPINTF 47 860#define CLK_VDO1_DISP_MONITOR_DPINTF 48 861#define CLK_VDO1_26M_SLOW 49 862#define CLK_VDO1_NR_CLK 50 863 864#endif /* _DT_BINDINGS_CLK_MT8195_H */