cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,dispcc-sc7280.h (1925B)


      1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      2/*
      3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
      4 */
      5
      6#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
      7#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
      8
      9/* DISP_CC clocks */
     10#define DISP_CC_PLL0					0
     11#define DISP_CC_MDSS_AHB_CLK				1
     12#define DISP_CC_MDSS_AHB_CLK_SRC			2
     13#define DISP_CC_MDSS_BYTE0_CLK				3
     14#define DISP_CC_MDSS_BYTE0_CLK_SRC			4
     15#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC			5
     16#define DISP_CC_MDSS_BYTE0_INTF_CLK			6
     17#define DISP_CC_MDSS_DP_AUX_CLK				7
     18#define DISP_CC_MDSS_DP_AUX_CLK_SRC			8
     19#define DISP_CC_MDSS_DP_CRYPTO_CLK			9
     20#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC			10
     21#define DISP_CC_MDSS_DP_LINK_CLK			11
     22#define DISP_CC_MDSS_DP_LINK_CLK_SRC			12
     23#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC		13
     24#define DISP_CC_MDSS_DP_LINK_INTF_CLK			14
     25#define DISP_CC_MDSS_DP_PIXEL_CLK			15
     26#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC			16
     27#define DISP_CC_MDSS_EDP_AUX_CLK			17
     28#define DISP_CC_MDSS_EDP_AUX_CLK_SRC			18
     29#define DISP_CC_MDSS_EDP_LINK_CLK			19
     30#define DISP_CC_MDSS_EDP_LINK_CLK_SRC			20
     31#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC		21
     32#define DISP_CC_MDSS_EDP_LINK_INTF_CLK			22
     33#define DISP_CC_MDSS_EDP_PIXEL_CLK			23
     34#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC			24
     35#define DISP_CC_MDSS_ESC0_CLK				25
     36#define DISP_CC_MDSS_ESC0_CLK_SRC			26
     37#define DISP_CC_MDSS_MDP_CLK				27
     38#define DISP_CC_MDSS_MDP_CLK_SRC			28
     39#define DISP_CC_MDSS_MDP_LUT_CLK			29
     40#define DISP_CC_MDSS_NON_GDSC_AHB_CLK			30
     41#define DISP_CC_MDSS_PCLK0_CLK				31
     42#define DISP_CC_MDSS_PCLK0_CLK_SRC			32
     43#define DISP_CC_MDSS_ROT_CLK				33
     44#define DISP_CC_MDSS_ROT_CLK_SRC			34
     45#define DISP_CC_MDSS_RSCC_AHB_CLK			35
     46#define DISP_CC_MDSS_RSCC_VSYNC_CLK			36
     47#define DISP_CC_MDSS_VSYNC_CLK				37
     48#define DISP_CC_MDSS_VSYNC_CLK_SRC			38
     49#define DISP_CC_SLEEP_CLK				39
     50#define DISP_CC_XO_CLK					40
     51
     52/* DISP_CC power domains */
     53#define DISP_CC_MDSS_CORE_GDSC				0
     54
     55#endif