r8a77970-cpg-mssr.h (1280B)
1/* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright (C) 2016 Renesas Electronics Corp. 4 * Copyright (C) 2017 Cogent Embedded, Inc. 5 */ 6#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 7#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 8 9#include <dt-bindings/clock/renesas-cpg-mssr.h> 10 11/* r8a77970 CPG Core Clocks */ 12#define R8A77970_CLK_Z2 0 13#define R8A77970_CLK_ZR 1 14#define R8A77970_CLK_ZTR 2 15#define R8A77970_CLK_ZTRD2 3 16#define R8A77970_CLK_ZT 4 17#define R8A77970_CLK_ZX 5 18#define R8A77970_CLK_S1D1 6 19#define R8A77970_CLK_S1D2 7 20#define R8A77970_CLK_S1D4 8 21#define R8A77970_CLK_S2D1 9 22#define R8A77970_CLK_S2D2 10 23#define R8A77970_CLK_S2D4 11 24#define R8A77970_CLK_LB 12 25#define R8A77970_CLK_CL 13 26#define R8A77970_CLK_ZB3 14 27#define R8A77970_CLK_ZB3D2 15 28#define R8A77970_CLK_DDR 16 29#define R8A77970_CLK_CR 17 30#define R8A77970_CLK_CRD2 18 31#define R8A77970_CLK_SD0H 19 32#define R8A77970_CLK_SD0 20 33#define R8A77970_CLK_RPC 21 34#define R8A77970_CLK_RPCD2 22 35#define R8A77970_CLK_MSO 23 36#define R8A77970_CLK_CANFD 24 37#define R8A77970_CLK_CSI0 25 38#define R8A77970_CLK_FRAY 26 39#define R8A77970_CLK_CP 27 40#define R8A77970_CLK_CPEX 28 41#define R8A77970_CLK_R 29 42#define R8A77970_CLK_OSC 30 43 44#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */