cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a779f0-cpg-mssr.h (1961B)


      1/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
      2/*
      3 * Copyright (C) 2021 Renesas Electronics Corp.
      4 */
      5#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
      6#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
      7
      8#include <dt-bindings/clock/renesas-cpg-mssr.h>
      9
     10/* r8a779f0 CPG Core Clocks */
     11
     12#define R8A779F0_CLK_ZX			0
     13#define R8A779F0_CLK_ZS			1
     14#define R8A779F0_CLK_ZT			2
     15#define R8A779F0_CLK_ZTR		3
     16#define R8A779F0_CLK_S0D2		4
     17#define R8A779F0_CLK_S0D3		5
     18#define R8A779F0_CLK_S0D4		6
     19#define R8A779F0_CLK_S0D2_MM		7
     20#define R8A779F0_CLK_S0D3_MM		8
     21#define R8A779F0_CLK_S0D4_MM		9
     22#define R8A779F0_CLK_S0D2_RT		10
     23#define R8A779F0_CLK_S0D3_RT		11
     24#define R8A779F0_CLK_S0D4_RT		12
     25#define R8A779F0_CLK_S0D6_RT		13
     26#define R8A779F0_CLK_S0D3_PER		14
     27#define R8A779F0_CLK_S0D6_PER		15
     28#define R8A779F0_CLK_S0D12_PER		16
     29#define R8A779F0_CLK_S0D24_PER		17
     30#define R8A779F0_CLK_S0D2_HSC		18
     31#define R8A779F0_CLK_S0D3_HSC		19
     32#define R8A779F0_CLK_S0D4_HSC		20
     33#define R8A779F0_CLK_S0D6_HSC		21
     34#define R8A779F0_CLK_S0D12_HSC		22
     35#define R8A779F0_CLK_S0D2_CC		23
     36#define R8A779F0_CLK_CL			24
     37#define R8A779F0_CLK_CL16M		25
     38#define R8A779F0_CLK_CL16M_MM		26
     39#define R8A779F0_CLK_CL16M_RT		27
     40#define R8A779F0_CLK_CL16M_PER		28
     41#define R8A779F0_CLK_CL16M_HSC		29
     42#define R8A779F0_CLK_Z0			30
     43#define R8A779F0_CLK_Z1			31
     44#define R8A779F0_CLK_ZB3		32
     45#define R8A779F0_CLK_ZB3D2		33
     46#define R8A779F0_CLK_ZB3D4		34
     47#define R8A779F0_CLK_SD0H		35
     48#define R8A779F0_CLK_SD0		36
     49#define R8A779F0_CLK_RPC		37
     50#define R8A779F0_CLK_RPCD2		38
     51#define R8A779F0_CLK_MSO		39
     52#define R8A779F0_CLK_SASYNCRT		40
     53#define R8A779F0_CLK_SASYNCPERD1	41
     54#define R8A779F0_CLK_SASYNCPERD2	42
     55#define R8A779F0_CLK_SASYNCPERD4	43
     56#define R8A779F0_CLK_DBGSOC_HSC		44
     57#define R8A779F0_CLK_RSW2		45
     58#define R8A779F0_CLK_OSC		46
     59#define R8A779F0_CLK_ZR			47
     60#define R8A779F0_CLK_CPEX		48
     61#define R8A779F0_CLK_CBFUSA		49
     62#define R8A779F0_CLK_R			50
     63
     64#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */