cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun8i-a23-a33-ccu.h (4056B)


      1/*
      2 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
      3 *
      4 * This file is dual-licensed: you can use it either under the terms
      5 * of the GPL or the X11 license, at your option. Note that this dual
      6 * licensing only applies to this file, and not this project as a
      7 * whole.
      8 *
      9 *  a) This file is free software; you can redistribute it and/or
     10 *     modify it under the terms of the GNU General Public License as
     11 *     published by the Free Software Foundation; either version 2 of the
     12 *     License, or (at your option) any later version.
     13 *
     14 *     This file is distributed in the hope that it will be useful,
     15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     17 *     GNU General Public License for more details.
     18 *
     19 * Or, alternatively,
     20 *
     21 *  b) Permission is hereby granted, free of charge, to any person
     22 *     obtaining a copy of this software and associated documentation
     23 *     files (the "Software"), to deal in the Software without
     24 *     restriction, including without limitation the rights to use,
     25 *     copy, modify, merge, publish, distribute, sublicense, and/or
     26 *     sell copies of the Software, and to permit persons to whom the
     27 *     Software is furnished to do so, subject to the following
     28 *     conditions:
     29 *
     30 *     The above copyright notice and this permission notice shall be
     31 *     included in all copies or substantial portions of the Software.
     32 *
     33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     40 *     OTHER DEALINGS IN THE SOFTWARE.
     41 */
     42
     43#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
     44#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
     45
     46#define CLK_PLL_MIPI		13
     47
     48#define CLK_CPUX		18
     49
     50#define CLK_BUS_MIPI_DSI	23
     51#define CLK_BUS_SS		24
     52#define CLK_BUS_DMA		25
     53#define CLK_BUS_MMC0		26
     54#define CLK_BUS_MMC1		27
     55#define CLK_BUS_MMC2		28
     56#define CLK_BUS_NAND		29
     57#define CLK_BUS_DRAM		30
     58#define CLK_BUS_HSTIMER		31
     59#define CLK_BUS_SPI0		32
     60#define CLK_BUS_SPI1		33
     61#define CLK_BUS_OTG		34
     62#define CLK_BUS_EHCI		35
     63#define CLK_BUS_OHCI		36
     64#define CLK_BUS_VE		37
     65#define CLK_BUS_LCD		38
     66#define CLK_BUS_CSI		39
     67#define CLK_BUS_DE_BE		40
     68#define CLK_BUS_DE_FE		41
     69#define CLK_BUS_GPU		42
     70#define CLK_BUS_MSGBOX		43
     71#define CLK_BUS_SPINLOCK	44
     72#define CLK_BUS_DRC		45
     73#define CLK_BUS_SAT		46
     74#define CLK_BUS_CODEC		47
     75#define CLK_BUS_PIO		48
     76#define CLK_BUS_I2S0		49
     77#define CLK_BUS_I2S1		50
     78#define CLK_BUS_I2C0		51
     79#define CLK_BUS_I2C1		52
     80#define CLK_BUS_I2C2		53
     81#define CLK_BUS_UART0		54
     82#define CLK_BUS_UART1		55
     83#define CLK_BUS_UART2		56
     84#define CLK_BUS_UART3		57
     85#define CLK_BUS_UART4		58
     86#define CLK_NAND		59
     87#define CLK_MMC0		60
     88#define CLK_MMC0_SAMPLE		61
     89#define CLK_MMC0_OUTPUT		62
     90#define CLK_MMC1		63
     91#define CLK_MMC1_SAMPLE		64
     92#define CLK_MMC1_OUTPUT		65
     93#define CLK_MMC2		66
     94#define CLK_MMC2_SAMPLE		67
     95#define CLK_MMC2_OUTPUT		68
     96#define CLK_SS			69
     97#define CLK_SPI0		70
     98#define CLK_SPI1		71
     99#define CLK_I2S0		72
    100#define CLK_I2S1		73
    101#define CLK_USB_PHY0		74
    102#define CLK_USB_PHY1		75
    103#define CLK_USB_HSIC		76
    104#define CLK_USB_HSIC_12M	77
    105#define CLK_USB_OHCI		78
    106
    107#define CLK_DRAM_VE		80
    108#define CLK_DRAM_CSI		81
    109#define CLK_DRAM_DRC		82
    110#define CLK_DRAM_DE_FE		83
    111#define CLK_DRAM_DE_BE		84
    112#define CLK_DE_BE		85
    113#define CLK_DE_FE		86
    114#define CLK_LCD_CH0		87
    115#define CLK_LCD_CH1		88
    116#define CLK_CSI_SCLK		89
    117#define CLK_CSI_MCLK		90
    118#define CLK_VE			91
    119#define CLK_AC_DIG		92
    120#define CLK_AC_DIG_4X		93
    121#define CLK_AVS			94
    122
    123#define CLK_DSI_SCLK		96
    124#define CLK_DSI_DPHY		97
    125#define CLK_DRC			98
    126#define CLK_GPU			99
    127#define CLK_ATS			100
    128
    129#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */