cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sun8i-v3s-ccu.h (3613B)


      1/*
      2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
      3 *
      4 * Based on sun8i-h3-ccu.h, which is:
      5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
      6 *
      7 * This file is dual-licensed: you can use it either under the terms
      8 * of the GPL or the X11 license, at your option. Note that this dual
      9 * licensing only applies to this file, and not this project as a
     10 * whole.
     11 *
     12 *  a) This file is free software; you can redistribute it and/or
     13 *     modify it under the terms of the GNU General Public License as
     14 *     published by the Free Software Foundation; either version 2 of the
     15 *     License, or (at your option) any later version.
     16 *
     17 *     This file is distributed in the hope that it will be useful,
     18 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
     19 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     20 *     GNU General Public License for more details.
     21 *
     22 * Or, alternatively,
     23 *
     24 *  b) Permission is hereby granted, free of charge, to any person
     25 *     obtaining a copy of this software and associated documentation
     26 *     files (the "Software"), to deal in the Software without
     27 *     restriction, including without limitation the rights to use,
     28 *     copy, modify, merge, publish, distribute, sublicense, and/or
     29 *     sell copies of the Software, and to permit persons to whom the
     30 *     Software is furnished to do so, subject to the following
     31 *     conditions:
     32 *
     33 *     The above copyright notice and this permission notice shall be
     34 *     included in all copies or substantial portions of the Software.
     35 *
     36 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     37 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
     38 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     39 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
     40 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     41 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     42 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     43 *     OTHER DEALINGS IN THE SOFTWARE.
     44 */
     45
     46#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
     47#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
     48
     49#define CLK_CPU			14
     50
     51#define CLK_BUS_CE		20
     52#define CLK_BUS_DMA		21
     53#define CLK_BUS_MMC0		22
     54#define CLK_BUS_MMC1		23
     55#define CLK_BUS_MMC2		24
     56#define CLK_BUS_DRAM		25
     57#define CLK_BUS_EMAC		26
     58#define CLK_BUS_HSTIMER		27
     59#define CLK_BUS_SPI0		28
     60#define CLK_BUS_OTG		29
     61#define CLK_BUS_EHCI0		30
     62#define CLK_BUS_OHCI0		31
     63#define CLK_BUS_VE		32
     64#define CLK_BUS_TCON0		33
     65#define CLK_BUS_CSI		34
     66#define CLK_BUS_DE		35
     67#define CLK_BUS_CODEC		36
     68#define CLK_BUS_PIO		37
     69#define CLK_BUS_I2C0		38
     70#define CLK_BUS_I2C1		39
     71#define CLK_BUS_UART0		40
     72#define CLK_BUS_UART1		41
     73#define CLK_BUS_UART2		42
     74#define CLK_BUS_EPHY		43
     75#define CLK_BUS_DBG		44
     76
     77#define CLK_MMC0		45
     78#define CLK_MMC0_SAMPLE		46
     79#define CLK_MMC0_OUTPUT		47
     80#define CLK_MMC1		48
     81#define CLK_MMC1_SAMPLE		49
     82#define CLK_MMC1_OUTPUT		50
     83#define CLK_MMC2		51
     84#define CLK_MMC2_SAMPLE		52
     85#define CLK_MMC2_OUTPUT		53
     86#define CLK_CE			54
     87#define CLK_SPI0		55
     88#define CLK_USB_PHY0		56
     89#define CLK_USB_OHCI0		57
     90
     91#define CLK_DRAM_VE		59
     92#define CLK_DRAM_CSI		60
     93#define CLK_DRAM_EHCI		61
     94#define CLK_DRAM_OHCI		62
     95#define CLK_DE			63
     96#define CLK_TCON0		64
     97#define CLK_CSI_MISC		65
     98#define CLK_CSI0_MCLK		66
     99#define CLK_CSI1_SCLK		67
    100#define CLK_CSI1_MCLK		68
    101#define CLK_VE			69
    102#define CLK_AC_DIG		70
    103#define CLK_AVS			71
    104
    105#define CLK_MIPI_CSI		73
    106
    107/* Clocks not available on V3s */
    108#define CLK_BUS_I2S0		75
    109#define CLK_I2S0		76
    110
    111#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */