tegra114-car.h (8180B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This header provides constants for binding nvidia,tegra114-car. 4 * 5 * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 6 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 8 * this case, those clocks are assigned IDs above 160 in order to highlight 9 * this issue. Implementations that interpret these clock IDs as bit values 10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 11 * explicitly handle these special cases. 12 * 13 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 14 * above. 15 */ 16 17#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 18#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 19 20/* 0 */ 21/* 1 */ 22/* 2 */ 23/* 3 */ 24#define TEGRA114_CLK_RTC 4 25#define TEGRA114_CLK_TIMER 5 26#define TEGRA114_CLK_UARTA 6 27/* 7 (register bit affects uartb and vfir) */ 28/* 8 */ 29#define TEGRA114_CLK_SDMMC2 9 30/* 10 (register bit affects spdif_in and spdif_out) */ 31#define TEGRA114_CLK_I2S1 11 32#define TEGRA114_CLK_I2C1 12 33#define TEGRA114_CLK_NDFLASH 13 34#define TEGRA114_CLK_SDMMC1 14 35#define TEGRA114_CLK_SDMMC4 15 36/* 16 */ 37#define TEGRA114_CLK_PWM 17 38#define TEGRA114_CLK_I2S2 18 39#define TEGRA114_CLK_EPP 19 40/* 20 (register bit affects vi and vi_sensor) */ 41#define TEGRA114_CLK_GR2D 21 42#define TEGRA114_CLK_USBD 22 43#define TEGRA114_CLK_ISP 23 44#define TEGRA114_CLK_GR3D 24 45/* 25 */ 46#define TEGRA114_CLK_DISP2 26 47#define TEGRA114_CLK_DISP1 27 48#define TEGRA114_CLK_HOST1X 28 49#define TEGRA114_CLK_VCP 29 50#define TEGRA114_CLK_I2S0 30 51/* 31 */ 52 53#define TEGRA114_CLK_MC 32 54/* 33 */ 55#define TEGRA114_CLK_APBDMA 34 56/* 35 */ 57#define TEGRA114_CLK_KBC 36 58/* 37 */ 59/* 38 */ 60/* 39 (register bit affects fuse and fuse_burn) */ 61#define TEGRA114_CLK_KFUSE 40 62#define TEGRA114_CLK_SBC1 41 63#define TEGRA114_CLK_NOR 42 64/* 43 */ 65#define TEGRA114_CLK_SBC2 44 66/* 45 */ 67#define TEGRA114_CLK_SBC3 46 68#define TEGRA114_CLK_I2C5 47 69#define TEGRA114_CLK_DSIA 48 70/* 49 */ 71#define TEGRA114_CLK_MIPI 50 72#define TEGRA114_CLK_HDMI 51 73#define TEGRA114_CLK_CSI 52 74/* 53 */ 75#define TEGRA114_CLK_I2C2 54 76#define TEGRA114_CLK_UARTC 55 77#define TEGRA114_CLK_MIPI_CAL 56 78#define TEGRA114_CLK_EMC 57 79#define TEGRA114_CLK_USB2 58 80#define TEGRA114_CLK_USB3 59 81/* 60 */ 82#define TEGRA114_CLK_VDE 61 83#define TEGRA114_CLK_BSEA 62 84#define TEGRA114_CLK_BSEV 63 85 86/* 64 */ 87#define TEGRA114_CLK_UARTD 65 88/* 66 */ 89#define TEGRA114_CLK_I2C3 67 90#define TEGRA114_CLK_SBC4 68 91#define TEGRA114_CLK_SDMMC3 69 92/* 70 */ 93#define TEGRA114_CLK_OWR 71 94/* 72 */ 95#define TEGRA114_CLK_CSITE 73 96/* 74 */ 97/* 75 */ 98#define TEGRA114_CLK_LA 76 99#define TEGRA114_CLK_TRACE 77 100#define TEGRA114_CLK_SOC_THERM 78 101#define TEGRA114_CLK_DTV 79 102#define TEGRA114_CLK_NDSPEED 80 103#define TEGRA114_CLK_I2CSLOW 81 104#define TEGRA114_CLK_DSIB 82 105#define TEGRA114_CLK_TSEC 83 106/* 84 */ 107/* 85 */ 108/* 86 */ 109/* 87 */ 110/* 88 */ 111#define TEGRA114_CLK_XUSB_HOST 89 112/* 90 */ 113#define TEGRA114_CLK_MSENC 91 114#define TEGRA114_CLK_CSUS 92 115/* 93 */ 116/* 94 */ 117/* 95 (bit affects xusb_dev and xusb_dev_src) */ 118 119/* 96 */ 120/* 97 */ 121/* 98 */ 122#define TEGRA114_CLK_MSELECT 99 123#define TEGRA114_CLK_TSENSOR 100 124#define TEGRA114_CLK_I2S3 101 125#define TEGRA114_CLK_I2S4 102 126#define TEGRA114_CLK_I2C4 103 127#define TEGRA114_CLK_SBC5 104 128#define TEGRA114_CLK_SBC6 105 129#define TEGRA114_CLK_D_AUDIO 106 130#define TEGRA114_CLK_APBIF 107 131#define TEGRA114_CLK_DAM0 108 132#define TEGRA114_CLK_DAM1 109 133#define TEGRA114_CLK_DAM2 110 134#define TEGRA114_CLK_HDA2CODEC_2X 111 135/* 112 */ 136#define TEGRA114_CLK_AUDIO0_2X 113 137#define TEGRA114_CLK_AUDIO1_2X 114 138#define TEGRA114_CLK_AUDIO2_2X 115 139#define TEGRA114_CLK_AUDIO3_2X 116 140#define TEGRA114_CLK_AUDIO4_2X 117 141#define TEGRA114_CLK_SPDIF_2X 118 142#define TEGRA114_CLK_ACTMON 119 143#define TEGRA114_CLK_EXTERN1 120 144#define TEGRA114_CLK_EXTERN2 121 145#define TEGRA114_CLK_EXTERN3 122 146/* 123 */ 147/* 124 */ 148#define TEGRA114_CLK_HDA 125 149/* 126 */ 150#define TEGRA114_CLK_SE 127 151 152#define TEGRA114_CLK_HDA2HDMI 128 153/* 129 */ 154/* 130 */ 155/* 131 */ 156/* 132 */ 157/* 133 */ 158/* 134 */ 159/* 135 */ 160#define TEGRA114_CLK_CEC 136 161/* 137 */ 162/* 138 */ 163/* 139 */ 164/* 140 */ 165/* 141 */ 166/* 142 */ 167/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 168/* xusb_host_src and xusb_ss_src) */ 169#define TEGRA114_CLK_CILAB 144 170#define TEGRA114_CLK_CILCD 145 171#define TEGRA114_CLK_CILE 146 172#define TEGRA114_CLK_DSIALP 147 173#define TEGRA114_CLK_DSIBLP 148 174/* 149 */ 175#define TEGRA114_CLK_DDS 150 176/* 151 */ 177#define TEGRA114_CLK_DP2 152 178#define TEGRA114_CLK_AMX 153 179#define TEGRA114_CLK_ADX 154 180/* 155 (bit affects dfll_ref and dfll_soc) */ 181#define TEGRA114_CLK_XUSB_SS 156 182/* 157 */ 183/* 158 */ 184/* 159 */ 185 186/* 160 */ 187/* 161 */ 188/* 162 */ 189/* 163 */ 190/* 164 */ 191/* 165 */ 192/* 166 */ 193/* 167 */ 194/* 168 */ 195/* 169 */ 196/* 170 */ 197/* 171 */ 198/* 172 */ 199/* 173 */ 200/* 174 */ 201/* 175 */ 202/* 176 */ 203/* 177 */ 204/* 178 */ 205/* 179 */ 206/* 180 */ 207/* 181 */ 208/* 182 */ 209/* 183 */ 210/* 184 */ 211/* 185 */ 212/* 186 */ 213/* 187 */ 214/* 188 */ 215/* 189 */ 216/* 190 */ 217/* 191 */ 218 219#define TEGRA114_CLK_UARTB 192 220#define TEGRA114_CLK_VFIR 193 221#define TEGRA114_CLK_SPDIF_IN 194 222#define TEGRA114_CLK_SPDIF_OUT 195 223#define TEGRA114_CLK_VI 196 224#define TEGRA114_CLK_VI_SENSOR 197 225#define TEGRA114_CLK_FUSE 198 226#define TEGRA114_CLK_FUSE_BURN 199 227#define TEGRA114_CLK_CLK_32K 200 228#define TEGRA114_CLK_CLK_M 201 229#define TEGRA114_CLK_CLK_M_DIV2 202 230#define TEGRA114_CLK_CLK_M_DIV4 203 231#define TEGRA114_CLK_OSC_DIV2 202 232#define TEGRA114_CLK_OSC_DIV4 203 233#define TEGRA114_CLK_PLL_REF 204 234#define TEGRA114_CLK_PLL_C 205 235#define TEGRA114_CLK_PLL_C_OUT1 206 236#define TEGRA114_CLK_PLL_C2 207 237#define TEGRA114_CLK_PLL_C3 208 238#define TEGRA114_CLK_PLL_M 209 239#define TEGRA114_CLK_PLL_M_OUT1 210 240#define TEGRA114_CLK_PLL_P 211 241#define TEGRA114_CLK_PLL_P_OUT1 212 242#define TEGRA114_CLK_PLL_P_OUT2 213 243#define TEGRA114_CLK_PLL_P_OUT3 214 244#define TEGRA114_CLK_PLL_P_OUT4 215 245#define TEGRA114_CLK_PLL_A 216 246#define TEGRA114_CLK_PLL_A_OUT0 217 247#define TEGRA114_CLK_PLL_D 218 248#define TEGRA114_CLK_PLL_D_OUT0 219 249#define TEGRA114_CLK_PLL_D2 220 250#define TEGRA114_CLK_PLL_D2_OUT0 221 251#define TEGRA114_CLK_PLL_U 222 252#define TEGRA114_CLK_PLL_U_480M 223 253 254#define TEGRA114_CLK_PLL_U_60M 224 255#define TEGRA114_CLK_PLL_U_48M 225 256#define TEGRA114_CLK_PLL_U_12M 226 257#define TEGRA114_CLK_PLL_X 227 258#define TEGRA114_CLK_PLL_X_OUT0 228 259#define TEGRA114_CLK_PLL_RE_VCO 229 260#define TEGRA114_CLK_PLL_RE_OUT 230 261#define TEGRA114_CLK_PLL_E_OUT0 231 262#define TEGRA114_CLK_SPDIF_IN_SYNC 232 263#define TEGRA114_CLK_I2S0_SYNC 233 264#define TEGRA114_CLK_I2S1_SYNC 234 265#define TEGRA114_CLK_I2S2_SYNC 235 266#define TEGRA114_CLK_I2S3_SYNC 236 267#define TEGRA114_CLK_I2S4_SYNC 237 268#define TEGRA114_CLK_VIMCLK_SYNC 238 269#define TEGRA114_CLK_AUDIO0 239 270#define TEGRA114_CLK_AUDIO1 240 271#define TEGRA114_CLK_AUDIO2 241 272#define TEGRA114_CLK_AUDIO3 242 273#define TEGRA114_CLK_AUDIO4 243 274#define TEGRA114_CLK_SPDIF 244 275/* 245 */ 276/* 246 */ 277/* 247 */ 278/* 248 */ 279#define TEGRA114_CLK_OSC 249 280/* 250 */ 281/* 251 */ 282#define TEGRA114_CLK_XUSB_HOST_SRC 252 283#define TEGRA114_CLK_XUSB_FALCON_SRC 253 284#define TEGRA114_CLK_XUSB_FS_SRC 254 285#define TEGRA114_CLK_XUSB_SS_SRC 255 286 287#define TEGRA114_CLK_XUSB_DEV_SRC 256 288#define TEGRA114_CLK_XUSB_DEV 257 289#define TEGRA114_CLK_XUSB_HS_SRC 258 290#define TEGRA114_CLK_SCLK 259 291#define TEGRA114_CLK_HCLK 260 292#define TEGRA114_CLK_PCLK 261 293#define TEGRA114_CLK_CCLK_G 262 294#define TEGRA114_CLK_CCLK_LP 263 295#define TEGRA114_CLK_DFLL_REF 264 296#define TEGRA114_CLK_DFLL_SOC 265 297/* 266 */ 298/* 267 */ 299/* 268 */ 300/* 269 */ 301/* 270 */ 302/* 271 */ 303/* 272 */ 304/* 273 */ 305/* 274 */ 306/* 275 */ 307/* 276 */ 308/* 277 */ 309/* 278 */ 310/* 279 */ 311/* 280 */ 312/* 281 */ 313/* 282 */ 314/* 283 */ 315/* 284 */ 316/* 285 */ 317/* 286 */ 318/* 287 */ 319 320/* 288 */ 321/* 289 */ 322/* 290 */ 323/* 291 */ 324/* 292 */ 325/* 293 */ 326/* 294 */ 327/* 295 */ 328/* 296 */ 329/* 297 */ 330/* 298 */ 331/* 299 */ 332#define TEGRA114_CLK_AUDIO0_MUX 300 333#define TEGRA114_CLK_AUDIO1_MUX 301 334#define TEGRA114_CLK_AUDIO2_MUX 302 335#define TEGRA114_CLK_AUDIO3_MUX 303 336#define TEGRA114_CLK_AUDIO4_MUX 304 337#define TEGRA114_CLK_SPDIF_MUX 305 338/* 306 */ 339/* 307 */ 340/* 308 */ 341#define TEGRA114_CLK_DSIA_MUX 309 342#define TEGRA114_CLK_DSIB_MUX 310 343#define TEGRA114_CLK_XUSB_SS_DIV2 311 344#define TEGRA114_CLK_CLK_MAX 312 345 346#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */