cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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x1830-dma.h (1131B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * This header provides macros for X1830 DMA bindings.
      4 *
      5 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
      6 */
      7
      8#ifndef __DT_BINDINGS_DMA_X1830_DMA_H__
      9#define __DT_BINDINGS_DMA_X1830_DMA_H__
     10
     11/*
     12 * Request type numbers for the X1830 DMA controller (written to the DRTn
     13 * register for the channel).
     14 */
     15#define X1830_DMA_I2S0_TX	0x6
     16#define X1830_DMA_I2S0_RX	0x7
     17#define X1830_DMA_AUTO		0x8
     18#define X1830_DMA_SADC_RX	0x9
     19#define X1830_DMA_UART1_TX	0x12
     20#define X1830_DMA_UART1_RX	0x13
     21#define X1830_DMA_UART0_TX	0x14
     22#define X1830_DMA_UART0_RX	0x15
     23#define X1830_DMA_SSI0_TX	0x16
     24#define X1830_DMA_SSI0_RX	0x17
     25#define X1830_DMA_SSI1_TX	0x18
     26#define X1830_DMA_SSI1_RX	0x19
     27#define X1830_DMA_MSC0_TX	0x1a
     28#define X1830_DMA_MSC0_RX	0x1b
     29#define X1830_DMA_MSC1_TX	0x1c
     30#define X1830_DMA_MSC1_RX	0x1d
     31#define X1830_DMA_DMIC_RX	0x21
     32#define X1830_DMA_SMB0_TX	0x24
     33#define X1830_DMA_SMB0_RX	0x25
     34#define X1830_DMA_SMB1_TX	0x26
     35#define X1830_DMA_SMB1_RX	0x27
     36#define X1830_DMA_DES_TX	0x2e
     37#define X1830_DMA_DES_RX	0x2f
     38
     39#endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */