cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx8mq.h (1048B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Interconnect framework driver for i.MX SoC
      4 *
      5 * Copyright (c) 2019-2020, NXP
      6 */
      7
      8#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
      9#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
     10
     11#define IMX8MQ_ICN_NOC		1
     12#define IMX8MQ_ICS_DRAM		2
     13#define IMX8MQ_ICS_OCRAM	3
     14#define IMX8MQ_ICM_A53		4
     15
     16#define IMX8MQ_ICM_VPU		5
     17#define IMX8MQ_ICN_VIDEO	6
     18
     19#define IMX8MQ_ICM_GPU		7
     20#define IMX8MQ_ICN_GPU		8
     21
     22#define IMX8MQ_ICM_DCSS		9
     23#define IMX8MQ_ICN_DCSS		10
     24
     25#define IMX8MQ_ICM_USB1		11
     26#define IMX8MQ_ICM_USB2		12
     27#define IMX8MQ_ICN_USB		13
     28
     29#define IMX8MQ_ICM_CSI1		14
     30#define IMX8MQ_ICM_CSI2		15
     31#define IMX8MQ_ICM_LCDIF	16
     32#define IMX8MQ_ICN_DISPLAY	17
     33
     34#define IMX8MQ_ICM_SDMA2	18
     35#define IMX8MQ_ICN_AUDIO	19
     36
     37#define IMX8MQ_ICN_ENET		20
     38#define IMX8MQ_ICM_ENET		21
     39
     40#define IMX8MQ_ICM_SDMA1	22
     41#define IMX8MQ_ICM_NAND		23
     42#define IMX8MQ_ICM_USDHC1	24
     43#define IMX8MQ_ICM_USDHC2	25
     44#define IMX8MQ_ICM_PCIE1	26
     45#define IMX8MQ_ICM_PCIE2	27
     46#define IMX8MQ_ICN_MAIN		28
     47
     48#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */