cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt2701-larb-port.h (3778B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2015 MediaTek Inc.
      4 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
      5 */
      6
      7#ifndef _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
      8#define _DT_BINDINGS_MEMORY_MT2701_LARB_PORT_H_
      9
     10/*
     11 * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
     12 * the first port's id for larb[N] would be the last port's id of larb[N - 1]
     13 * plus one while larb[0]'s first port number is 0. The definition of
     14 * MT2701_M4U_ID_LARBx is following HW register spec.
     15 * But m4u generation 2 like mt8173 have different port number, it use fixed
     16 * offset for each larb, the first port's id for larb[N] would be (N * 32).
     17 */
     18#define LARB0_PORT_OFFSET		0
     19#define LARB1_PORT_OFFSET		11
     20#define LARB2_PORT_OFFSET		21
     21#define LARB3_PORT_OFFSET		44
     22
     23#define MT2701_M4U_ID_LARB0(port)	((port) + LARB0_PORT_OFFSET)
     24#define MT2701_M4U_ID_LARB1(port)	((port) + LARB1_PORT_OFFSET)
     25#define MT2701_M4U_ID_LARB2(port)	((port) + LARB2_PORT_OFFSET)
     26
     27/* Port define for larb0 */
     28#define MT2701_M4U_PORT_DISP_OVL_0		MT2701_M4U_ID_LARB0(0)
     29#define MT2701_M4U_PORT_DISP_RDMA1		MT2701_M4U_ID_LARB0(1)
     30#define MT2701_M4U_PORT_DISP_RDMA		MT2701_M4U_ID_LARB0(2)
     31#define MT2701_M4U_PORT_DISP_WDMA		MT2701_M4U_ID_LARB0(3)
     32#define MT2701_M4U_PORT_MM_CMDQ			MT2701_M4U_ID_LARB0(4)
     33#define MT2701_M4U_PORT_MDP_RDMA		MT2701_M4U_ID_LARB0(5)
     34#define MT2701_M4U_PORT_MDP_WDMA		MT2701_M4U_ID_LARB0(6)
     35#define MT2701_M4U_PORT_MDP_ROTO		MT2701_M4U_ID_LARB0(7)
     36#define MT2701_M4U_PORT_MDP_ROTCO		MT2701_M4U_ID_LARB0(8)
     37#define MT2701_M4U_PORT_MDP_ROTVO		MT2701_M4U_ID_LARB0(9)
     38#define MT2701_M4U_PORT_MDP_RDMA1		MT2701_M4U_ID_LARB0(10)
     39
     40/* Port define for larb1 */
     41#define MT2701_M4U_PORT_VDEC_MC_EXT		MT2701_M4U_ID_LARB1(0)
     42#define MT2701_M4U_PORT_VDEC_PP_EXT		MT2701_M4U_ID_LARB1(1)
     43#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT		MT2701_M4U_ID_LARB1(2)
     44#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT		MT2701_M4U_ID_LARB1(3)
     45#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT	MT2701_M4U_ID_LARB1(4)
     46#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT	MT2701_M4U_ID_LARB1(5)
     47#define MT2701_M4U_PORT_VDEC_VLD_EXT		MT2701_M4U_ID_LARB1(6)
     48#define MT2701_M4U_PORT_VDEC_VLD2_EXT		MT2701_M4U_ID_LARB1(7)
     49#define MT2701_M4U_PORT_VDEC_TILE_EXT		MT2701_M4U_ID_LARB1(8)
     50#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT	MT2701_M4U_ID_LARB1(9)
     51
     52/* Port define for larb2 */
     53#define MT2701_M4U_PORT_VENC_RCPU		MT2701_M4U_ID_LARB2(0)
     54#define MT2701_M4U_PORT_VENC_REC_FRM		MT2701_M4U_ID_LARB2(1)
     55#define MT2701_M4U_PORT_VENC_BSDMA		MT2701_M4U_ID_LARB2(2)
     56#define MT2701_M4U_PORT_JPGENC_RDMA		MT2701_M4U_ID_LARB2(3)
     57#define MT2701_M4U_PORT_VENC_LT_RCPU		MT2701_M4U_ID_LARB2(4)
     58#define MT2701_M4U_PORT_VENC_LT_REC_FRM		MT2701_M4U_ID_LARB2(5)
     59#define MT2701_M4U_PORT_VENC_LT_BSDMA		MT2701_M4U_ID_LARB2(6)
     60#define MT2701_M4U_PORT_JPGDEC_BSDMA		MT2701_M4U_ID_LARB2(7)
     61#define MT2701_M4U_PORT_VENC_SV_COMV		MT2701_M4U_ID_LARB2(8)
     62#define MT2701_M4U_PORT_VENC_RD_COMV		MT2701_M4U_ID_LARB2(9)
     63#define MT2701_M4U_PORT_JPGENC_BSDMA		MT2701_M4U_ID_LARB2(10)
     64#define MT2701_M4U_PORT_VENC_CUR_LUMA		MT2701_M4U_ID_LARB2(11)
     65#define MT2701_M4U_PORT_VENC_CUR_CHROMA		MT2701_M4U_ID_LARB2(12)
     66#define MT2701_M4U_PORT_VENC_REF_LUMA		MT2701_M4U_ID_LARB2(13)
     67#define MT2701_M4U_PORT_VENC_REF_CHROMA		MT2701_M4U_ID_LARB2(14)
     68#define MT2701_M4U_PORT_IMG_RESZ		MT2701_M4U_ID_LARB2(15)
     69#define MT2701_M4U_PORT_VENC_LT_SV_COMV		MT2701_M4U_ID_LARB2(16)
     70#define MT2701_M4U_PORT_VENC_LT_RD_COMV		MT2701_M4U_ID_LARB2(17)
     71#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA	MT2701_M4U_ID_LARB2(18)
     72#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA	MT2701_M4U_ID_LARB2(19)
     73#define MT2701_M4U_PORT_VENC_LT_REF_LUMA	MT2701_M4U_ID_LARB2(20)
     74#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA	MT2701_M4U_ID_LARB2(21)
     75#define MT2701_M4U_PORT_JPGDEC_WDMA		MT2701_M4U_ID_LARB2(22)
     76
     77#endif