cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra234-mc.h (3419B)


      1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
      2/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
      3
      4#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
      5#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
      6
      7/* special clients */
      8#define TEGRA234_SID_INVALID		0x00
      9#define TEGRA234_SID_PASSTHROUGH	0x7f
     10
     11/* NISO0 stream IDs */
     12#define TEGRA234_SID_APE	0x02
     13#define TEGRA234_SID_HDA	0x03
     14#define TEGRA234_SID_PCIE0	0x12
     15#define TEGRA234_SID_PCIE4	0x13
     16#define TEGRA234_SID_PCIE5	0x14
     17#define TEGRA234_SID_PCIE6	0x15
     18#define TEGRA234_SID_PCIE9	0x1f
     19
     20/* NISO1 stream IDs */
     21#define TEGRA234_SID_SDMMC4	0x02
     22#define TEGRA234_SID_PCIE1	0x05
     23#define TEGRA234_SID_PCIE2	0x06
     24#define TEGRA234_SID_PCIE3	0x07
     25#define TEGRA234_SID_PCIE7	0x08
     26#define TEGRA234_SID_PCIE8	0x09
     27#define TEGRA234_SID_PCIE10	0x0b
     28#define TEGRA234_SID_BPMP	0x10
     29
     30/*
     31 * memory client IDs
     32 */
     33
     34/* High-definition audio (HDA) read clients */
     35#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
     36/* PCIE6 read clients */
     37#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
     38/* PCIE6 write clients */
     39#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
     40/* PCIE7 read clients */
     41#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
     42/* PCIE7 write clients */
     43#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
     44/* PCIE8 read clients */
     45#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
     46/* High-definition audio (HDA) write clients */
     47#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
     48/* PCIE8 write clients */
     49#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
     50/* PCIE9 read clients */
     51#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
     52/* PCIE6r1 read clients */
     53#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
     54/* PCIE9 write clients */
     55#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
     56/* PCIE10 read clients */
     57#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
     58/* PCIE10 write clients */
     59#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
     60/* PCIE10r1 read clients */
     61#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
     62/* PCIE7r1 read clients */
     63#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
     64/* sdmmcd memory read client */
     65#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
     66/* sdmmcd memory write client */
     67#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
     68/* BPMP read client */
     69#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
     70/* BPMP write client */
     71#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
     72/* BPMPDMA read client */
     73#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
     74/* BPMPDMA write client */
     75#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
     76/* APEDMA read client */
     77#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
     78/* APEDMA write client */
     79#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
     80/* PCIE0 read clients */
     81#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
     82/* PCIE0 write clients */
     83#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
     84/* PCIE1 read clients */
     85#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
     86/* PCIE1 write clients */
     87#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
     88/* PCIE2 read clients */
     89#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
     90/* PCIE2 write clients */
     91#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
     92/* PCIE3 read clients */
     93#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
     94/* PCIE3 write clients */
     95#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
     96/* PCIE4 read clients */
     97#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
     98/* PCIE4 write clients */
     99#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
    100/* PCIE5 read clients */
    101#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
    102/* PCIE5 write clients */
    103#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
    104/* PCIE5r1 read clients */
    105#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
    106
    107#endif