ti-serdes.h (3891B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This header provides constants for SERDES MUX for TI SoCs 4 */ 5 6#ifndef _DT_BINDINGS_MUX_TI_SERDES 7#define _DT_BINDINGS_MUX_TI_SERDES 8 9/* J721E */ 10 11#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 12#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 13#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 14#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 15 16#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 17#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 18#define J721E_SERDES0_LANE1_USB3_0 0x2 19#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 20 21#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 22#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 23#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 24#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 25 26#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 27#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 28#define J721E_SERDES1_LANE1_USB3_1 0x2 29#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 30 31#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 32#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 33#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 34#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 35 36#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 37#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 38#define J721E_SERDES2_LANE1_USB3_1 0x2 39#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 40 41#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 42#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 43#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 44#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 45 46#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 47#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 48#define J721E_SERDES3_LANE1_USB3_0 0x2 49#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 50 51#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 52#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 53#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 54#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 55 56#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 57#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 58#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 59#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 60 61#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 62#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 63#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 64#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 65 66#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 67#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 68#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 69#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 70 71/* J7200 */ 72 73#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 74#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 75#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 76#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 77 78#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 79#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 80#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 81#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 82 83#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 84#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 85#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 86#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 87 88#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 89#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 90#define J7200_SERDES0_LANE3_USB 0x2 91#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 92 93/* AM64 */ 94 95#define AM64_SERDES0_LANE0_PCIE0 0x0 96#define AM64_SERDES0_LANE0_USB 0x1 97 98/* J721S2 */ 99 100#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 101#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 102#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 103#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 104 105#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 106#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 107#define J721S2_SERDES0_LANE1_USB 0x2 108#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 109 110#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 111#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 112#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 113#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 114 115#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 116#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 117#define J721S2_SERDES0_LANE3_USB 0x2 118#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 119 120#endif /* _DT_BINDINGS_MUX_TI_SERDES */