ti-dp83869.h (1382B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Device Tree constants for the Texas Instruments DP83869 PHY 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 7 * Copyright: (C) 2019 Texas Instruments, Inc. 8 */ 9 10#ifndef _DT_BINDINGS_TI_DP83869_H 11#define _DT_BINDINGS_TI_DP83869_H 12 13/* PHY CTRL bits */ 14#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 15#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 16#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 17#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 18 19/* IO_MUX_CFG - Clock output selection */ 20#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 21#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 22#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 23#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 24#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 25#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 26#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 27#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 28#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 29#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 30#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa 31#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb 32#define DP83869_CLK_O_SEL_REF_CLK 0xc 33 34#define DP83869_RGMII_COPPER_ETHERNET 0x00 35#define DP83869_RGMII_1000_BASE 0x01 36#define DP83869_RGMII_100_BASE 0x02 37#define DP83869_RGMII_SGMII_BRIDGE 0x03 38#define DP83869_1000M_MEDIA_CONVERT 0x04 39#define DP83869_100M_MEDIA_CONVERT 0x05 40#define DP83869_SGMII_COPPER_ETHERNET 0x06 41 42#endif