cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r7s9210-pinctrl.h (1124B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Defines macros and constants for Renesas RZ/A2 pin controller pin
      4 * muxing functions.
      5 */
      6#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
      7#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H
      8
      9#define RZA2_PINS_PER_PORT	8
     10
     11/* Port names as labeled in the Hardware Manual */
     12#define PORT0 0
     13#define PORT1 1
     14#define PORT2 2
     15#define PORT3 3
     16#define PORT4 4
     17#define PORT5 5
     18#define PORT6 6
     19#define PORT7 7
     20#define PORT8 8
     21#define PORT9 9
     22#define PORTA 10
     23#define PORTB 11
     24#define PORTC 12
     25#define PORTD 13
     26#define PORTE 14
     27#define PORTF 15
     28#define PORTG 16
     29#define PORTH 17
     30/* No I */
     31#define PORTJ 18
     32#define PORTK 19
     33#define PORTL 20
     34#define PORTM 21	/* Pins PM_0/1 are labeled JP_0/1 in HW manual */
     35
     36/*
     37 * Create the pin index from its bank and position numbers and store in
     38 * the upper 16 bits the alternate function identifier
     39 */
     40#define RZA2_PINMUX(b, p, f)	((b) * RZA2_PINS_PER_PORT + (p) | (f << 16))
     41
     42/*
     43 * Convert a port and pin label to its global pin index
     44 */
     45 #define RZA2_PIN(port, pin)	((port) * RZA2_PINS_PER_PORT + (pin))
     46
     47#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */