cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a7795-sysc.h (1141B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2016 Glider bvba
      4 */
      5#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
      6#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
      7
      8/*
      9 * These power domain indices match the numbers of the interrupt bits
     10 * representing the power areas in the various Interrupt Registers
     11 * (e.g. SYSCISR, Interrupt Status Register)
     12 */
     13
     14#define R8A7795_PD_CA57_CPU0		 0
     15#define R8A7795_PD_CA57_CPU1		 1
     16#define R8A7795_PD_CA57_CPU2		 2
     17#define R8A7795_PD_CA57_CPU3		 3
     18#define R8A7795_PD_CA53_CPU0		 5
     19#define R8A7795_PD_CA53_CPU1		 6
     20#define R8A7795_PD_CA53_CPU2		 7
     21#define R8A7795_PD_CA53_CPU3		 8
     22#define R8A7795_PD_A3VP			 9
     23#define R8A7795_PD_CA57_SCU		12
     24#define R8A7795_PD_CR7			13
     25#define R8A7795_PD_A3VC			14
     26#define R8A7795_PD_3DG_A		17
     27#define R8A7795_PD_3DG_B		18
     28#define R8A7795_PD_3DG_C		19
     29#define R8A7795_PD_3DG_D		20
     30#define R8A7795_PD_CA53_SCU		21
     31#define R8A7795_PD_3DG_E		22
     32#define R8A7795_PD_A3IR			24
     33#define R8A7795_PD_A2VC0		25	/* ES1.x only */
     34#define R8A7795_PD_A2VC1		26
     35
     36/* Always-on power area */
     37#define R8A7795_PD_ALWAYS_ON		32
     38
     39#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */