cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a779a0-sysc.h (1714B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2020 Renesas Electronics Corp.
      4 */
      5#ifndef __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
      6#define __DT_BINDINGS_POWER_R8A779A0_SYSC_H__
      7
      8/*
      9 * These power domain indices match the Power Domain Register Numbers (PDR)
     10 */
     11
     12#define R8A779A0_PD_A1E0D0C0		0
     13#define R8A779A0_PD_A1E0D0C1		1
     14#define R8A779A0_PD_A1E0D1C0		2
     15#define R8A779A0_PD_A1E0D1C1		3
     16#define R8A779A0_PD_A1E1D0C0		4
     17#define R8A779A0_PD_A1E1D0C1		5
     18#define R8A779A0_PD_A1E1D1C0		6
     19#define R8A779A0_PD_A1E1D1C1		7
     20#define R8A779A0_PD_A2E0D0		16
     21#define R8A779A0_PD_A2E0D1		17
     22#define R8A779A0_PD_A2E1D0		18
     23#define R8A779A0_PD_A2E1D1		19
     24#define R8A779A0_PD_A3E0		20
     25#define R8A779A0_PD_A3E1		21
     26#define R8A779A0_PD_3DG_A		24
     27#define R8A779A0_PD_3DG_B		25
     28#define R8A779A0_PD_A1CNN2		32
     29#define R8A779A0_PD_A1DSP0		33
     30#define R8A779A0_PD_A2IMP01		34
     31#define R8A779A0_PD_A2DP0		35
     32#define R8A779A0_PD_A2CV0		36
     33#define R8A779A0_PD_A2CV1		37
     34#define R8A779A0_PD_A2CV4		38
     35#define R8A779A0_PD_A2CV6		39
     36#define R8A779A0_PD_A2CN2		40
     37#define R8A779A0_PD_A1CNN0		41
     38#define R8A779A0_PD_A2CN0		42
     39#define R8A779A0_PD_A3IR		43
     40#define R8A779A0_PD_A1CNN1		44
     41#define R8A779A0_PD_A1DSP1		45
     42#define R8A779A0_PD_A2IMP23		46
     43#define R8A779A0_PD_A2DP1		47
     44#define R8A779A0_PD_A2CV2		48
     45#define R8A779A0_PD_A2CV3		49
     46#define R8A779A0_PD_A2CV5		50
     47#define R8A779A0_PD_A2CV7		51
     48#define R8A779A0_PD_A2CN1		52
     49#define R8A779A0_PD_A3VIP0		56
     50#define R8A779A0_PD_A3VIP1		57
     51#define R8A779A0_PD_A3VIP2		58
     52#define R8A779A0_PD_A3VIP3		59
     53#define R8A779A0_PD_A3ISP01		60
     54#define R8A779A0_PD_A3ISP23		61
     55
     56/* Always-on power area */
     57#define R8A779A0_PD_ALWAYS_ON		64
     58
     59#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__ */