mt7629-resets.h (2206B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2019 MediaTek Inc. 4 */ 5 6#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629 7#define _DT_BINDINGS_RESET_CONTROLLER_MT7629 8 9/* INFRACFG resets */ 10#define MT7629_INFRA_EMI_MPU_RST 0 11#define MT7629_INFRA_UART5_RST 2 12#define MT7629_INFRA_CIRQ_EINT_RST 3 13#define MT7629_INFRA_APXGPT_RST 4 14#define MT7629_INFRA_SCPSYS_RST 5 15#define MT7629_INFRA_KP_RST 6 16#define MT7629_INFRA_SPI1_RST 7 17#define MT7629_INFRA_SPI4_RST 8 18#define MT7629_INFRA_SYSTIMER_RST 9 19#define MT7629_INFRA_IRRX_RST 10 20#define MT7629_INFRA_AO_BUS_RST 16 21#define MT7629_INFRA_EMI_RST 32 22#define MT7629_INFRA_APMIXED_RST 35 23#define MT7629_INFRA_MIPI_RST 36 24#define MT7629_INFRA_TRNG_RST 37 25#define MT7629_INFRA_SYSCIRQ_RST 38 26#define MT7629_INFRA_MIPI_CSI_RST 39 27#define MT7629_INFRA_GCE_FAXI_RST 40 28#define MT7629_INFRA_I2C_SRAM_RST 41 29#define MT7629_INFRA_IOMMU_RST 47 30 31/* PERICFG resets */ 32#define MT7629_PERI_UART0_SW_RST 0 33#define MT7629_PERI_UART1_SW_RST 1 34#define MT7629_PERI_UART2_SW_RST 2 35#define MT7629_PERI_BTIF_SW_RST 6 36#define MT7629_PERI_PWN_SW_RST 8 37#define MT7629_PERI_DMA_SW_RST 11 38#define MT7629_PERI_NFI_SW_RST 14 39#define MT7629_PERI_I2C0_SW_RST 22 40#define MT7629_PERI_SPI0_SW_RST 33 41#define MT7629_PERI_SPI1_SW_RST 34 42#define MT7629_PERI_FLASHIF_SW_RST 36 43 44/* PCIe Subsystem resets */ 45#define MT7629_PCIE1_CORE_RST 19 46#define MT7629_PCIE1_MMIO_RST 20 47#define MT7629_PCIE1_HRST 21 48#define MT7629_PCIE1_USER_RST 22 49#define MT7629_PCIE1_PIPE_RST 23 50#define MT7629_PCIE0_CORE_RST 27 51#define MT7629_PCIE0_MMIO_RST 28 52#define MT7629_PCIE0_HRST 29 53#define MT7629_PCIE0_USER_RST 30 54#define MT7629_PCIE0_PIPE_RST 31 55 56/* SSUSB Subsystem resets */ 57#define MT7629_SSUSB_PHY_PWR_RST 3 58#define MT7629_SSUSB_MAC_PWR_RST 4 59 60/* ETH Subsystem resets */ 61#define MT7629_ETHSYS_SYS_RST 0 62#define MT7629_ETHSYS_MCM_RST 2 63#define MT7629_ETHSYS_HSDMA_RST 5 64#define MT7629_ETHSYS_FE_RST 6 65#define MT7629_ETHSYS_ESW_RST 16 66#define MT7629_ETHSYS_GMAC_RST 23 67#define MT7629_ETHSYS_EPHY_RST 24 68#define MT7629_ETHSYS_CRYPTO_RST 29 69#define MT7629_ETHSYS_PPE_RST 31 70 71#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */