cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nuvoton,npcm7xx-reset.h (2805B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2// Copyright (c) 2019 Nuvoton Technology corporation.
      3
      4#ifndef _DT_BINDINGS_NPCM7XX_RESET_H
      5#define _DT_BINDINGS_NPCM7XX_RESET_H
      6
      7#define NPCM7XX_RESET_IPSRST1		0x20
      8#define NPCM7XX_RESET_IPSRST2		0x24
      9#define NPCM7XX_RESET_IPSRST3		0x34
     10
     11/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
     12#define NPCM7XX_RESET_FIU3		1
     13#define NPCM7XX_RESET_UDC1		5
     14#define NPCM7XX_RESET_EMC1		6
     15#define NPCM7XX_RESET_UART_2_3		7
     16#define NPCM7XX_RESET_UDC2		8
     17#define NPCM7XX_RESET_PECI		9
     18#define NPCM7XX_RESET_AES		10
     19#define NPCM7XX_RESET_UART_0_1		11
     20#define NPCM7XX_RESET_MC		12
     21#define NPCM7XX_RESET_SMB2		13
     22#define NPCM7XX_RESET_SMB3		14
     23#define NPCM7XX_RESET_SMB4		15
     24#define NPCM7XX_RESET_SMB5		16
     25#define NPCM7XX_RESET_PWM_M0		18
     26#define NPCM7XX_RESET_TIMER_0_4		19
     27#define NPCM7XX_RESET_TIMER_5_9		20
     28#define NPCM7XX_RESET_EMC2		21
     29#define NPCM7XX_RESET_UDC4		22
     30#define NPCM7XX_RESET_UDC5		23
     31#define NPCM7XX_RESET_UDC6		24
     32#define NPCM7XX_RESET_UDC3		25
     33#define NPCM7XX_RESET_ADC		27
     34#define NPCM7XX_RESET_SMB6		28
     35#define NPCM7XX_RESET_SMB7		29
     36#define NPCM7XX_RESET_SMB0		30
     37#define NPCM7XX_RESET_SMB1		31
     38
     39/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
     40#define NPCM7XX_RESET_MFT0		0
     41#define NPCM7XX_RESET_MFT1		1
     42#define NPCM7XX_RESET_MFT2		2
     43#define NPCM7XX_RESET_MFT3		3
     44#define NPCM7XX_RESET_MFT4		4
     45#define NPCM7XX_RESET_MFT5		5
     46#define NPCM7XX_RESET_MFT6		6
     47#define NPCM7XX_RESET_MFT7		7
     48#define NPCM7XX_RESET_MMC		8
     49#define NPCM7XX_RESET_SDHC		9
     50#define NPCM7XX_RESET_GFX_SYS		10
     51#define NPCM7XX_RESET_AHB_PCIBRG	11
     52#define NPCM7XX_RESET_VDMA		12
     53#define NPCM7XX_RESET_ECE		13
     54#define NPCM7XX_RESET_VCD		14
     55#define NPCM7XX_RESET_OTP		16
     56#define NPCM7XX_RESET_SIOX1		18
     57#define NPCM7XX_RESET_SIOX2		19
     58#define NPCM7XX_RESET_3DES		21
     59#define NPCM7XX_RESET_PSPI1		22
     60#define NPCM7XX_RESET_PSPI2		23
     61#define NPCM7XX_RESET_GMAC2		25
     62#define NPCM7XX_RESET_USB_HOST		26
     63#define NPCM7XX_RESET_GMAC1		28
     64#define NPCM7XX_RESET_CP		31
     65
     66/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
     67#define NPCM7XX_RESET_PWM_M1		0
     68#define NPCM7XX_RESET_SMB12		1
     69#define NPCM7XX_RESET_SPIX		2
     70#define NPCM7XX_RESET_SMB13		3
     71#define NPCM7XX_RESET_UDC0		4
     72#define NPCM7XX_RESET_UDC7		5
     73#define NPCM7XX_RESET_UDC8		6
     74#define NPCM7XX_RESET_UDC9		7
     75#define NPCM7XX_RESET_PCI_MAILBOX	9
     76#define NPCM7XX_RESET_SMB14		12
     77#define NPCM7XX_RESET_SHA		13
     78#define NPCM7XX_RESET_SEC_ECC		14
     79#define NPCM7XX_RESET_PCIE_RC		15
     80#define NPCM7XX_RESET_TIMER_10_14	16
     81#define NPCM7XX_RESET_RNG		17
     82#define NPCM7XX_RESET_SMB15		18
     83#define NPCM7XX_RESET_SMB8		19
     84#define NPCM7XX_RESET_SMB9		20
     85#define NPCM7XX_RESET_SMB10		21
     86#define NPCM7XX_RESET_SMB11		22
     87#define NPCM7XX_RESET_ESPI		23
     88#define NPCM7XX_RESET_USB_PHY_1		24
     89#define NPCM7XX_RESET_USB_PHY_2		25
     90
     91#endif