cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sun20i-d1-ccu.h (1985B)


      1/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
      2/*
      3 * Copyright (c) 2020 huangzhenwei@allwinnertech.com
      4 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
      5 */
      6
      7#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
      8#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
      9
     10#define RST_MBUS		0
     11#define RST_BUS_DE		1
     12#define RST_BUS_DI		2
     13#define RST_BUS_G2D		3
     14#define RST_BUS_CE		4
     15#define RST_BUS_VE		5
     16#define RST_BUS_DMA		6
     17#define RST_BUS_MSGBOX0		7
     18#define RST_BUS_MSGBOX1		8
     19#define RST_BUS_MSGBOX2		9
     20#define RST_BUS_SPINLOCK	10
     21#define RST_BUS_HSTIMER		11
     22#define RST_BUS_DBG		12
     23#define RST_BUS_PWM		13
     24#define RST_BUS_DRAM		14
     25#define RST_BUS_MMC0		15
     26#define RST_BUS_MMC1		16
     27#define RST_BUS_MMC2		17
     28#define RST_BUS_UART0		18
     29#define RST_BUS_UART1		19
     30#define RST_BUS_UART2		20
     31#define RST_BUS_UART3		21
     32#define RST_BUS_UART4		22
     33#define RST_BUS_UART5		23
     34#define RST_BUS_I2C0		24
     35#define RST_BUS_I2C1		25
     36#define RST_BUS_I2C2		26
     37#define RST_BUS_I2C3		27
     38#define RST_BUS_SPI0		28
     39#define RST_BUS_SPI1		29
     40#define RST_BUS_EMAC		30
     41#define RST_BUS_IR_TX		31
     42#define RST_BUS_GPADC		32
     43#define RST_BUS_THS		33
     44#define RST_BUS_I2S0		34
     45#define RST_BUS_I2S1		35
     46#define RST_BUS_I2S2		36
     47#define RST_BUS_SPDIF		37
     48#define RST_BUS_DMIC		38
     49#define RST_BUS_AUDIO		39
     50#define RST_USB_PHY0		40
     51#define RST_USB_PHY1		41
     52#define RST_BUS_OHCI0		42
     53#define RST_BUS_OHCI1		43
     54#define RST_BUS_EHCI0		44
     55#define RST_BUS_EHCI1		45
     56#define RST_BUS_OTG		46
     57#define RST_BUS_LRADC		47
     58#define RST_BUS_DPSS_TOP	48
     59#define RST_BUS_HDMI_SUB	49
     60#define RST_BUS_HDMI_MAIN	50
     61#define RST_BUS_MIPI_DSI	51
     62#define RST_BUS_TCON_LCD0	52
     63#define RST_BUS_TCON_TV		53
     64#define RST_BUS_LVDS0		54
     65#define RST_BUS_TVE		55
     66#define RST_BUS_TVE_TOP		56
     67#define RST_BUS_TVD		57
     68#define RST_BUS_TVD_TOP		58
     69#define RST_BUS_LEDC		59
     70#define RST_BUS_CSI		60
     71#define RST_BUS_TPADC		61
     72#define RST_DSP			62
     73#define RST_BUS_DSP_CFG		63
     74#define RST_BUS_DSP_DBG		64
     75#define RST_BUS_RISCV_CFG	65
     76
     77#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */