cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cs42l42.h (1926B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * cs42l42.h -- CS42L42 ALSA SoC audio driver DT bindings header
      4 *
      5 * Copyright 2016 Cirrus Logic, Inc.
      6 *
      7 * Author: James Schulman <james.schulman@cirrus.com>
      8 * Author: Brian Austin <brian.austin@cirrus.com>
      9 * Author: Michael White <michael.white@cirrus.com>
     10 */
     11
     12#ifndef __DT_CS42L42_H
     13#define __DT_CS42L42_H
     14
     15/* HPOUT Load Capacity */
     16#define CS42L42_HPOUT_LOAD_1NF		0
     17#define CS42L42_HPOUT_LOAD_10NF		1
     18
     19/* HPOUT Clamp to GND Override */
     20#define CS42L42_HPOUT_CLAMP_EN		0
     21#define CS42L42_HPOUT_CLAMP_DIS		1
     22
     23/* Tip Sense Inversion */
     24#define CS42L42_TS_INV_DIS			0
     25#define CS42L42_TS_INV_EN			1
     26
     27/* Tip Sense Debounce */
     28#define CS42L42_TS_DBNCE_0			0
     29#define CS42L42_TS_DBNCE_125			1
     30#define CS42L42_TS_DBNCE_250			2
     31#define CS42L42_TS_DBNCE_500			3
     32#define CS42L42_TS_DBNCE_750			4
     33#define CS42L42_TS_DBNCE_1000			5
     34#define CS42L42_TS_DBNCE_1250			6
     35#define CS42L42_TS_DBNCE_1500			7
     36
     37/* Button Press Software Debounce Times */
     38#define CS42L42_BTN_DET_INIT_DBNCE_MIN		0
     39#define CS42L42_BTN_DET_INIT_DBNCE_DEFAULT	100
     40#define CS42L42_BTN_DET_INIT_DBNCE_MAX		200
     41
     42#define CS42L42_BTN_DET_EVENT_DBNCE_MIN		0
     43#define CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT	10
     44#define CS42L42_BTN_DET_EVENT_DBNCE_MAX		20
     45
     46/* Button Detect Level Sensitivities */
     47#define CS42L42_NUM_BIASES		4
     48
     49#define CS42L42_HS_DET_LEVEL_15		0x0F
     50#define CS42L42_HS_DET_LEVEL_8		0x08
     51#define CS42L42_HS_DET_LEVEL_4		0x04
     52#define CS42L42_HS_DET_LEVEL_1		0x01
     53
     54#define CS42L42_HS_DET_LEVEL_MIN	0
     55#define CS42L42_HS_DET_LEVEL_MAX	0x3F
     56
     57/* HS Bias Ramp Rate */
     58
     59#define CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL		0
     60#define CS42L42_HSBIAS_RAMP_FAST			1
     61#define CS42L42_HSBIAS_RAMP_SLOW			2
     62#define CS42L42_HSBIAS_RAMP_SLOWEST			3
     63
     64#define CS42L42_HSBIAS_RAMP_TIME0			10
     65#define CS42L42_HSBIAS_RAMP_TIME1			40
     66#define CS42L42_HSBIAS_RAMP_TIME2			90
     67#define CS42L42_HSBIAS_RAMP_TIME3			170
     68
     69#endif /* __DT_CS42L42_H */