cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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adreno-smmu-priv.h (2807B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2020 Google, Inc
      4 */
      5
      6#ifndef __ADRENO_SMMU_PRIV_H
      7#define __ADRENO_SMMU_PRIV_H
      8
      9#include <linux/io-pgtable.h>
     10
     11/**
     12 * struct adreno_smmu_fault_info - container for key fault information
     13 *
     14 * @far: The faulting IOVA from ARM_SMMU_CB_FAR
     15 * @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
     16 * @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
     17 * @fsr: The fault status from ARM_SMMU_CB_FSR
     18 * @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
     19 * @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
     20 * @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
     21 *
     22 * This struct passes back key page fault information to the GPU driver
     23 * through the get_fault_info function pointer.
     24 * The GPU driver can use this information to print informative
     25 * log messages and provide deeper GPU specific insight into the fault.
     26 */
     27struct adreno_smmu_fault_info {
     28	u64 far;
     29	u64 ttbr0;
     30	u32 contextidr;
     31	u32 fsr;
     32	u32 fsynr0;
     33	u32 fsynr1;
     34	u32 cbfrsynra;
     35};
     36
     37/**
     38 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
     39 *
     40 * @cookie:        An opque token provided by adreno-smmu and passed
     41 *                 back into the callbacks
     42 * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank
     43 * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank.  A
     44 *                 NULL config disables TTBR0 translation, otherwise
     45 *                 TTBR0 translation is enabled with the specified cfg
     46 * @get_fault_info: Called by the GPU fault handler to get information about
     47 *                  the fault
     48 * @set_stall:     Configure whether stall on fault (CFCFG) is enabled.  Call
     49 *                 before set_ttbr0_cfg().  If stalling on fault is enabled,
     50 *                 the GPU driver must call resume_translation()
     51 * @resume_translation: Resume translation after a fault
     52 *
     53 *
     54 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
     55 * the GPU's SMMU instance.  This is by necessity, as the GPU is directly
     56 * updating the SMMU for context switches, while on the other hand we do
     57 * not want to duplicate all of the initial setup logic from arm-smmu.
     58 *
     59 * This private interface is used for the two drivers to coordinate.  The
     60 * cookie and callback functions are populated when the GPU driver attaches
     61 * it's domain.
     62 */
     63struct adreno_smmu_priv {
     64    const void *cookie;
     65    const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
     66    int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
     67    void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
     68    void (*set_stall)(const void *cookie, bool enabled);
     69    void (*resume_translation)(const void *cookie, bool terminate);
     70};
     71
     72#endif /* __ADRENO_SMMU_PRIV_H */