cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

kmi.h (2272B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 *  linux/include/asm-arm/hardware/amba_kmi.h
      4 *
      5 *  Internal header file for AMBA KMI ports
      6 *
      7 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
      8 *
      9 * ---------------------------------------------------------------------------
     10 *  From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
     11 *  Reference Manual - ARM DDI 0143B - see http://www.arm.com/
     12 * ---------------------------------------------------------------------------
     13 */
     14#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
     15#define ASM_ARM_HARDWARE_AMBA_KMI_H
     16
     17/*
     18 * KMI control register:
     19 *  KMICR_TYPE       0 = PS2/AT mode, 1 = No line control bit mode
     20 *  KMICR_RXINTREN   1 = enable RX interrupts
     21 *  KMICR_TXINTREN   1 = enable TX interrupts
     22 *  KMICR_EN         1 = enable KMI
     23 *  KMICR_FD         1 = force KMI data low
     24 *  KMICR_FC         1 = force KMI clock low
     25 */
     26#define KMICR		(KMI_BASE + 0x00)
     27#define KMICR_TYPE		(1 << 5)
     28#define KMICR_RXINTREN		(1 << 4)
     29#define KMICR_TXINTREN		(1 << 3)
     30#define KMICR_EN		(1 << 2)
     31#define KMICR_FD		(1 << 1)
     32#define KMICR_FC		(1 << 0)
     33
     34/*
     35 * KMI status register:
     36 *  KMISTAT_TXEMPTY  1 = transmitter register empty
     37 *  KMISTAT_TXBUSY   1 = currently sending data
     38 *  KMISTAT_RXFULL   1 = receiver register ready to be read
     39 *  KMISTAT_RXBUSY   1 = currently receiving data
     40 *  KMISTAT_RXPARITY parity of last databyte received
     41 *  KMISTAT_IC       current level of KMI clock input
     42 *  KMISTAT_ID       current level of KMI data input
     43 */
     44#define KMISTAT		(KMI_BASE + 0x04)
     45#define KMISTAT_TXEMPTY		(1 << 6)
     46#define KMISTAT_TXBUSY		(1 << 5)
     47#define KMISTAT_RXFULL		(1 << 4)
     48#define KMISTAT_RXBUSY		(1 << 3)
     49#define KMISTAT_RXPARITY	(1 << 2)
     50#define KMISTAT_IC		(1 << 1)
     51#define KMISTAT_ID		(1 << 0)
     52
     53/*
     54 * KMI data register
     55 */
     56#define KMIDATA		(KMI_BASE + 0x08)
     57
     58/*
     59 * KMI clock divisor: to generate 8MHz internal clock
     60 *  div = (ref / 8MHz) - 1; 0 <= div <= 15
     61 */
     62#define KMICLKDIV	(KMI_BASE + 0x0c)
     63
     64/*
     65 * KMI interrupt register:
     66 *  KMIIR_TXINTR     1 = transmit interrupt asserted
     67 *  KMIIR_RXINTR     1 = receive interrupt asserted
     68 */
     69#define KMIIR		(KMI_BASE + 0x10)
     70#define KMIIR_TXINTR		(1 << 1)
     71#define KMIIR_RXINTR		(1 << 0)
     72
     73/*
     74 * The size of the KMI primecell
     75 */
     76#define KMI_SIZE	(0x100)
     77
     78#endif