brcmphy.h (14476B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _LINUX_BRCMPHY_H 3#define _LINUX_BRCMPHY_H 4 5#include <linux/phy.h> 6 7/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used 8 * to configure the switch internal registers via MDIO accesses. 9 */ 10#define BRCM_PSEUDO_PHY_ADDR 30 11 12#define PHY_ID_BCM50610 0x0143bd60 13#define PHY_ID_BCM50610M 0x0143bd70 14#define PHY_ID_BCM5241 0x0143bc30 15#define PHY_ID_BCMAC131 0x0143bc70 16#define PHY_ID_BCM5481 0x0143bca0 17#define PHY_ID_BCM5395 0x0143bcf0 18#define PHY_ID_BCM53125 0x03625f20 19#define PHY_ID_BCM54810 0x03625d00 20#define PHY_ID_BCM54811 0x03625cc0 21#define PHY_ID_BCM5482 0x0143bcb0 22#define PHY_ID_BCM5411 0x00206070 23#define PHY_ID_BCM5421 0x002060e0 24#define PHY_ID_BCM54210E 0x600d84a0 25#define PHY_ID_BCM5464 0x002060b0 26#define PHY_ID_BCM5461 0x002060c0 27#define PHY_ID_BCM54612E 0x03625e60 28#define PHY_ID_BCM54616S 0x03625d10 29#define PHY_ID_BCM54140 0xae025009 30#define PHY_ID_BCM57780 0x03625d90 31#define PHY_ID_BCM89610 0x03625cd0 32 33#define PHY_ID_BCM72113 0x35905310 34#define PHY_ID_BCM72116 0x35905350 35#define PHY_ID_BCM72165 0x35905340 36#define PHY_ID_BCM7250 0xae025280 37#define PHY_ID_BCM7255 0xae025120 38#define PHY_ID_BCM7260 0xae025190 39#define PHY_ID_BCM7268 0xae025090 40#define PHY_ID_BCM7271 0xae0253b0 41#define PHY_ID_BCM7278 0xae0251a0 42#define PHY_ID_BCM7364 0xae025260 43#define PHY_ID_BCM7366 0x600d8490 44#define PHY_ID_BCM7346 0x600d8650 45#define PHY_ID_BCM7362 0x600d84b0 46#define PHY_ID_BCM7425 0x600d86b0 47#define PHY_ID_BCM7429 0x600d8730 48#define PHY_ID_BCM7435 0x600d8750 49#define PHY_ID_BCM74371 0xae0252e0 50#define PHY_ID_BCM7439 0x600d8480 51#define PHY_ID_BCM7439_2 0xae025080 52#define PHY_ID_BCM7445 0x600d8510 53#define PHY_ID_BCM7712 0x35905330 54 55#define PHY_ID_BCM_CYGNUS 0xae025200 56#define PHY_ID_BCM_OMEGA 0xae025100 57 58#define PHY_BCM_OUI_MASK 0xfffffc00 59#define PHY_BCM_OUI_1 0x00206000 60#define PHY_BCM_OUI_2 0x0143bc00 61#define PHY_BCM_OUI_3 0x03625c00 62#define PHY_BCM_OUI_4 0x600d8400 63#define PHY_BCM_OUI_5 0x03625e00 64#define PHY_BCM_OUI_6 0xae025000 65 66#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000001 67#define PHY_BRCM_RX_REFCLK_UNUSED 0x00000002 68#define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004 69#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008 70#define PHY_BRCM_EN_MASTER_MODE 0x00000010 71#define PHY_BRCM_IDDQ_SUSPEND 0x00000020 72 73/* Broadcom BCM7xxx specific workarounds */ 74#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) 75#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) 76#define PHY_BCM_FLAGS_VALID 0x80000000 77 78/* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 79#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 80#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 81#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 82#define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */ 83 84#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 85#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 86 87#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 88#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 89#define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */ 90#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 91#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 92#define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */ 93 94#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 95#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 96#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 97#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 98#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 99#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 100#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 101#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 102#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 103#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 104#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 105#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 106#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 107#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 108#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 109#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 110#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 111#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 112 113#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 114#define MII_BCM54XX_SHD_WRITE 0x8000 115#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 116#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 117 118#define MII_BCM54XX_RDB_ADDR 0x1e 119#define MII_BCM54XX_RDB_DATA 0x1f 120 121/* legacy access control via rdb/expansion register */ 122#define BCM54XX_RDB_REG0087 0x0087 123#define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E) 124#define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15) 125 126/* 127 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 128 */ 129#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00 130#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 131#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 132#define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000 133 134#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07 135#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 136#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080 137#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 138#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 139#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 140 141#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 142#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 143 144/* 145 * Broadcom LED source encodings. These are used in BCM5461, BCM5481, 146 * BCM5482, and possibly some others. 147 */ 148#define BCM_LED_SRC_LINKSPD1 0x0 149#define BCM_LED_SRC_LINKSPD2 0x1 150#define BCM_LED_SRC_XMITLED 0x2 151#define BCM_LED_SRC_ACTIVITYLED 0x3 152#define BCM_LED_SRC_FDXLED 0x4 153#define BCM_LED_SRC_SLAVE 0x5 154#define BCM_LED_SRC_INTR 0x6 155#define BCM_LED_SRC_QUALITY 0x7 156#define BCM_LED_SRC_RCVLED 0x8 157#define BCM_LED_SRC_WIRESPEED 0x9 158#define BCM_LED_SRC_MULTICOLOR1 0xa 159#define BCM_LED_SRC_OPENSHORT 0xb 160#define BCM_LED_SRC_OFF 0xe /* Tied high */ 161#define BCM_LED_SRC_ON 0xf /* Tied low */ 162 163/* 164 * Broadcom Multicolor LED configurations (expansion register 4) 165 */ 166#define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04) 167#define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) 168#define BCM_LED_MULTICOLOR_LINK_ACT 0x0 169#define BCM_LED_MULTICOLOR_SPEED 0x1 170#define BCM_LED_MULTICOLOR_ACT_FLASH 0x2 171#define BCM_LED_MULTICOLOR_FDX 0x3 172#define BCM_LED_MULTICOLOR_OFF 0x4 173#define BCM_LED_MULTICOLOR_ON 0x5 174#define BCM_LED_MULTICOLOR_ALT 0x6 175#define BCM_LED_MULTICOLOR_FLASH 0x7 176#define BCM_LED_MULTICOLOR_LINK 0x8 177#define BCM_LED_MULTICOLOR_ACT 0x9 178#define BCM_LED_MULTICOLOR_PROGRAM 0xa 179 180/* 181 * BCM5482: Shadow registers 182 * Shadow values go into bits [14:10] of register 0x1c to select a shadow 183 * register to access. 184 */ 185 186/* 00100: Reserved control register 2 */ 187#define BCM54XX_SHD_SCR2 0x04 188#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 189#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 190#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 191#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 192 193/* 00101: Spare Control Register 3 */ 194#define BCM54XX_SHD_SCR3 0x05 195#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 196#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 197#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 198#define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100 199 200/* 01010: Auto Power-Down */ 201#define BCM54XX_SHD_APD 0x0a 202#define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ 203#define BCM54XX_SHD_APD_EN 0x0020 204#define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ 205#define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ 206 207#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ 208 /* LED3 / ~LINKSPD[2] selector */ 209#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) 210 /* LED1 / ~LINKSPD[1] selector */ 211#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) 212#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ 213#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ 214#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ 215#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ 216 217/* 10011: SerDes 100-FX Control Register */ 218#define BCM54616S_SHD_100FX_CTRL 0x13 219#define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */ 220 221/* 11111: Mode Control Register */ 222#define BCM54XX_SHD_MODE 0x1f 223#define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */ 224#define BCM54XX_SHD_INTF_SEL_RGMII 0x02 225#define BCM54XX_SHD_INTF_SEL_SGMII 0x04 226#define BCM54XX_SHD_INTF_SEL_GBIC 0x06 227#define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */ 228 229/* 230 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) 231 */ 232#define MII_BCM54XX_EXP_AADJ1CH0 0x001f 233#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 234#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 235#define MII_BCM54XX_EXP_AADJ1CH3 0x601f 236#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 237#define MII_BCM54XX_EXP_EXP08 0x0F08 238#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 239#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 240#define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE 0x0100 241#define MII_BCM54XX_EXP_EXP75 0x0f75 242#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c 243#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 244#define MII_BCM54XX_EXP_EXP96 0x0f96 245#define MII_BCM54XX_EXP_EXP96_MYST 0x0010 246#define MII_BCM54XX_EXP_EXP97 0x0f97 247#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c 248 249/* Top-MISC expansion registers */ 250#define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06) 251#define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0) 252#define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2) 253#define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3) 254 255/* 256 * BCM5482: Secondary SerDes registers 257 */ 258#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ 259#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ 260#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ 261#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ 262#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ 263 264/* BCM54810 Registers */ 265#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90) 266#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0) 267#define BCM54810_SHD_CLK_CTL 0x3 268#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9) 269 270/* BCM54612E Registers */ 271#define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) 272#define BCM54612E_LED4_CLK125OUT_EN (1 << 1) 273 274/*****************************************************************************/ 275/* Fast Ethernet Transceiver definitions. */ 276/*****************************************************************************/ 277 278#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ 279#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ 280#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ 281#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ 282#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ 283#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ 284 285#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ 286#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ 287 288 289/*** Shadow register definitions ***/ 290 291#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ 292#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ 293 294#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ 295#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 296#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 297 298#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ 299#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ 300 301#define BRCM_CL45VEN_EEE_CONTROL 0x803d 302#define LPI_FEATURE_EN 0x8000 303#define LPI_FEATURE_EN_DIG1000X 0x4000 304 305/* Core register definitions*/ 306#define MII_BRCM_CORE_BASE12 0x12 307#define MII_BRCM_CORE_BASE13 0x13 308#define MII_BRCM_CORE_BASE14 0x14 309#define MII_BRCM_CORE_BASE1E 0x1E 310#define MII_BRCM_CORE_EXPB0 0xB0 311#define MII_BRCM_CORE_EXPB1 0xB1 312 313/* Enhanced Cable Diagnostics */ 314#define BCM54XX_RDB_ECD_CTRL 0x2a0 315#define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0) 316 317#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */ 318#define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */ 319#define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */ 320#define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */ 321#define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */ 322#define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */ 323#define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */ 324#define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */ 325#define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link 326 * during test 327 */ 328#define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair 329 * short check 330 */ 331#define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */ 332 333#define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1 334#define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1) 335#define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0 336#define BCM54XX_ECD_FAULT_TYPE_OK 0x1 337#define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2 338#define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */ 339#define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */ 340#define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9 341#define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0) 342#define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4) 343#define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8) 344#define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12) 345#define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 346#define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 347#define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 348#define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 349 350#define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 351#define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2) 352#define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 353#define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3) 354#define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 355#define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4) 356#define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 357#define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5) 358#define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff 359 360#endif /* _LINUX_BRCMPHY_H */