cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cacheinfo.h (3814B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _LINUX_CACHEINFO_H
      3#define _LINUX_CACHEINFO_H
      4
      5#include <linux/bitops.h>
      6#include <linux/cpumask.h>
      7#include <linux/smp.h>
      8
      9struct device_node;
     10struct attribute;
     11
     12enum cache_type {
     13	CACHE_TYPE_NOCACHE = 0,
     14	CACHE_TYPE_INST = BIT(0),
     15	CACHE_TYPE_DATA = BIT(1),
     16	CACHE_TYPE_SEPARATE = CACHE_TYPE_INST | CACHE_TYPE_DATA,
     17	CACHE_TYPE_UNIFIED = BIT(2),
     18};
     19
     20extern unsigned int coherency_max_size;
     21
     22/**
     23 * struct cacheinfo - represent a cache leaf node
     24 * @id: This cache's id. It is unique among caches with the same (type, level).
     25 * @type: type of the cache - data, inst or unified
     26 * @level: represents the hierarchy in the multi-level cache
     27 * @coherency_line_size: size of each cache line usually representing
     28 *	the minimum amount of data that gets transferred from memory
     29 * @number_of_sets: total number of sets, a set is a collection of cache
     30 *	lines sharing the same index
     31 * @ways_of_associativity: number of ways in which a particular memory
     32 *	block can be placed in the cache
     33 * @physical_line_partition: number of physical cache lines sharing the
     34 *	same cachetag
     35 * @size: Total size of the cache
     36 * @shared_cpu_map: logical cpumask representing all the cpus sharing
     37 *	this cache node
     38 * @attributes: bitfield representing various cache attributes
     39 * @fw_token: Unique value used to determine if different cacheinfo
     40 *	structures represent a single hardware cache instance.
     41 * @disable_sysfs: indicates whether this node is visible to the user via
     42 *	sysfs or not
     43 * @priv: pointer to any private data structure specific to particular
     44 *	cache design
     45 *
     46 * While @of_node, @disable_sysfs and @priv are used for internal book
     47 * keeping, the remaining members form the core properties of the cache
     48 */
     49struct cacheinfo {
     50	unsigned int id;
     51	enum cache_type type;
     52	unsigned int level;
     53	unsigned int coherency_line_size;
     54	unsigned int number_of_sets;
     55	unsigned int ways_of_associativity;
     56	unsigned int physical_line_partition;
     57	unsigned int size;
     58	cpumask_t shared_cpu_map;
     59	unsigned int attributes;
     60#define CACHE_WRITE_THROUGH	BIT(0)
     61#define CACHE_WRITE_BACK	BIT(1)
     62#define CACHE_WRITE_POLICY_MASK		\
     63	(CACHE_WRITE_THROUGH | CACHE_WRITE_BACK)
     64#define CACHE_READ_ALLOCATE	BIT(2)
     65#define CACHE_WRITE_ALLOCATE	BIT(3)
     66#define CACHE_ALLOCATE_POLICY_MASK	\
     67	(CACHE_READ_ALLOCATE | CACHE_WRITE_ALLOCATE)
     68#define CACHE_ID		BIT(4)
     69	void *fw_token;
     70	bool disable_sysfs;
     71	void *priv;
     72};
     73
     74struct cpu_cacheinfo {
     75	struct cacheinfo *info_list;
     76	unsigned int num_levels;
     77	unsigned int num_leaves;
     78	bool cpu_map_populated;
     79};
     80
     81struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
     82int init_cache_level(unsigned int cpu);
     83int populate_cache_leaves(unsigned int cpu);
     84int cache_setup_acpi(unsigned int cpu);
     85#ifndef CONFIG_ACPI_PPTT
     86/*
     87 * acpi_find_last_cache_level is only called on ACPI enabled
     88 * platforms using the PPTT for topology. This means that if
     89 * the platform supports other firmware configuration methods
     90 * we need to stub out the call when ACPI is disabled.
     91 * ACPI enabled platforms not using PPTT won't be making calls
     92 * to this function so we need not worry about them.
     93 */
     94static inline int acpi_find_last_cache_level(unsigned int cpu)
     95{
     96	return 0;
     97}
     98#else
     99int acpi_find_last_cache_level(unsigned int cpu);
    100#endif
    101
    102const struct attribute_group *cache_get_priv_group(struct cacheinfo *this_leaf);
    103
    104/*
    105 * Get the id of the cache associated with @cpu at level @level.
    106 * cpuhp lock must be held.
    107 */
    108static inline int get_cpu_cacheinfo_id(int cpu, int level)
    109{
    110	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
    111	int i;
    112
    113	for (i = 0; i < ci->num_leaves; i++) {
    114		if (ci->info_list[i].level == level) {
    115			if (ci->info_list[i].attributes & CACHE_ID)
    116				return ci->info_list[i].id;
    117			return -1;
    118		}
    119	}
    120
    121	return -1;
    122}
    123
    124#endif /* _LINUX_CACHEINFO_H */