cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

ti.h (13048B)


      1/*
      2 * TI clock drivers support
      3 *
      4 * Copyright (C) 2013 Texas Instruments, Inc.
      5 *
      6 * This program is free software; you can redistribute it and/or modify
      7 * it under the terms of the GNU General Public License version 2 as
      8 * published by the Free Software Foundation.
      9 *
     10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
     11 * kind, whether express or implied; without even the implied warranty
     12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13 * GNU General Public License for more details.
     14 */
     15#ifndef __LINUX_CLK_TI_H__
     16#define __LINUX_CLK_TI_H__
     17
     18#include <linux/clk-provider.h>
     19#include <linux/clkdev.h>
     20
     21/**
     22 * struct clk_omap_reg - OMAP register declaration
     23 * @offset: offset from the master IP module base address
     24 * @index: index of the master IP module
     25 */
     26struct clk_omap_reg {
     27	void __iomem *ptr;
     28	u16 offset;
     29	u8 index;
     30	u8 flags;
     31};
     32
     33/**
     34 * struct dpll_data - DPLL registers and integration data
     35 * @mult_div1_reg: register containing the DPLL M and N bitfields
     36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
     37 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
     38 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
     39 * @clk_ref: struct clk_hw pointer to the clock's reference clock input
     40 * @control_reg: register containing the DPLL mode bitfield
     41 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
     42 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
     43 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
     44 * @last_rounded_m4xen: cache of the last M4X result of
     45 *			omap4_dpll_regm4xen_round_rate()
     46 * @last_rounded_lpmode: cache of the last lpmode result of
     47 *			 omap4_dpll_lpmode_recalc()
     48 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
     49 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
     50 * @min_divider: minimum valid non-bypass divider value (actual)
     51 * @max_divider: maximum valid non-bypass divider value (actual)
     52 * @max_rate: maximum clock rate for the DPLL
     53 * @modes: possible values of @enable_mask
     54 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
     55 * @idlest_reg: register containing the DPLL idle status bitfield
     56 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
     57 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
     58 * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
     59 * @dcc_rate: rate atleast which DCC @dcc_mask must be set
     60 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
     61 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
     62 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
     63 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
     64 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
     65 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
     66 * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
     67 * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
     68 * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
     69 * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
     70 * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
     71 * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
     72 *                       @control_reg
     73 * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
     74 * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
     75 * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
     76 *                   mode
     77 * @flags: DPLL type/features (see below)
     78 *
     79 * Possible values for @flags:
     80 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
     81 *
     82 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
     83 *
     84 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
     85 * correct to only have one @clk_bypass pointer.
     86 *
     87 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
     88 * @last_rounded_n) should be separated from the runtime-fixed fields
     89 * and placed into a different structure, so that the runtime-fixed data
     90 * can be placed into read-only space.
     91 */
     92struct dpll_data {
     93	struct clk_omap_reg	mult_div1_reg;
     94	u32			mult_mask;
     95	u32			div1_mask;
     96	struct clk_hw		*clk_bypass;
     97	struct clk_hw		*clk_ref;
     98	struct clk_omap_reg	control_reg;
     99	u32			enable_mask;
    100	unsigned long		last_rounded_rate;
    101	u16			last_rounded_m;
    102	u8			last_rounded_m4xen;
    103	u8			last_rounded_lpmode;
    104	u16			max_multiplier;
    105	u8			last_rounded_n;
    106	u8			min_divider;
    107	u16			max_divider;
    108	unsigned long		max_rate;
    109	u8			modes;
    110	struct clk_omap_reg	autoidle_reg;
    111	struct clk_omap_reg	idlest_reg;
    112	u32			autoidle_mask;
    113	u32			freqsel_mask;
    114	u32			idlest_mask;
    115	u32			dco_mask;
    116	u32			sddiv_mask;
    117	u32			dcc_mask;
    118	unsigned long		dcc_rate;
    119	u32			lpmode_mask;
    120	u32			m4xen_mask;
    121	u8			auto_recal_bit;
    122	u8			recal_en_bit;
    123	u8			recal_st_bit;
    124	struct clk_omap_reg	ssc_deltam_reg;
    125	struct clk_omap_reg	ssc_modfreq_reg;
    126	u32			ssc_deltam_int_mask;
    127	u32			ssc_deltam_frac_mask;
    128	u32			ssc_modfreq_mant_mask;
    129	u32			ssc_modfreq_exp_mask;
    130	u32                     ssc_enable_mask;
    131	u32                     ssc_downspread_mask;
    132	u32                     ssc_modfreq;
    133	u32                     ssc_deltam;
    134	bool                    ssc_downspread;
    135	u8			flags;
    136};
    137
    138struct clk_hw_omap;
    139
    140/**
    141 * struct clk_hw_omap_ops - OMAP clk ops
    142 * @find_idlest: find idlest register information for a clock
    143 * @find_companion: find companion clock register information for a clock,
    144 *		    basically converts CM_ICLKEN* <-> CM_FCLKEN*
    145 * @allow_idle: enables autoidle hardware functionality for a clock
    146 * @deny_idle: prevent autoidle hardware functionality for a clock
    147 */
    148struct clk_hw_omap_ops {
    149	void	(*find_idlest)(struct clk_hw_omap *oclk,
    150			       struct clk_omap_reg *idlest_reg,
    151			       u8 *idlest_bit, u8 *idlest_val);
    152	void	(*find_companion)(struct clk_hw_omap *oclk,
    153				  struct clk_omap_reg *other_reg,
    154				  u8 *other_bit);
    155	void	(*allow_idle)(struct clk_hw_omap *oclk);
    156	void	(*deny_idle)(struct clk_hw_omap *oclk);
    157};
    158
    159/**
    160 * struct clk_hw_omap - OMAP struct clk
    161 * @node: list_head connecting this clock into the full clock list
    162 * @enable_reg: register to write to enable the clock (see @enable_bit)
    163 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
    164 * @flags: see "struct clk.flags possibilities" above
    165 * @clksel_reg: for clksel clks, register va containing src/divisor select
    166 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
    167 * @clkdm_name: clockdomain name that this clock is contained in
    168 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
    169 * @ops: clock ops for this clock
    170 */
    171struct clk_hw_omap {
    172	struct clk_hw		hw;
    173	struct list_head	node;
    174	unsigned long		fixed_rate;
    175	u8			fixed_div;
    176	struct clk_omap_reg	enable_reg;
    177	u8			enable_bit;
    178	unsigned long		flags;
    179	struct clk_omap_reg	clksel_reg;
    180	struct dpll_data	*dpll_data;
    181	const char		*clkdm_name;
    182	struct clockdomain	*clkdm;
    183	const struct clk_hw_omap_ops	*ops;
    184	u32			context;
    185	int			autoidle_count;
    186};
    187
    188/*
    189 * struct clk_hw_omap.flags possibilities
    190 *
    191 * XXX document the rest of the clock flags here
    192 *
    193 * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
    194 *     with 32bit ops, by default OMAP1 uses 16bit ops.
    195 * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
    196 * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
    197 *     clock is put to no-idle mode.
    198 * ENABLE_ON_INIT: Clock is enabled on init.
    199 * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
    200 *     disable. This inverts the behavior making '0' enable and '1' disable.
    201 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
    202 *     bits share the same register.  This flag allows the
    203 *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
    204 *     should be used.  This is a temporary solution - a better approach
    205 *     would be to associate clock type-specific data with the clock,
    206 *     similar to the struct dpll_data approach.
    207 */
    208#define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
    209#define CLOCK_IDLE_CONTROL	(1 << 1)
    210#define CLOCK_NO_IDLE_PARENT	(1 << 2)
    211#define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
    212#define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
    213#define CLOCK_CLKOUTX2		(1 << 5)
    214
    215/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
    216#define DPLL_LOW_POWER_STOP	0x1
    217#define DPLL_LOW_POWER_BYPASS	0x5
    218#define DPLL_LOCKED		0x7
    219
    220/* DPLL Type and DCO Selection Flags */
    221#define DPLL_J_TYPE		0x1
    222
    223/* Static memmap indices */
    224enum {
    225	TI_CLKM_CM = 0,
    226	TI_CLKM_CM2,
    227	TI_CLKM_PRM,
    228	TI_CLKM_SCRM,
    229	TI_CLKM_CTRL,
    230	TI_CLKM_CTRL_AUX,
    231	TI_CLKM_PLLSS,
    232	CLK_MAX_MEMMAPS
    233};
    234
    235/**
    236 * struct ti_clk_ll_ops - low-level ops for clocks
    237 * @clk_readl: pointer to register read function
    238 * @clk_writel: pointer to register write function
    239 * @clk_rmw: pointer to register read-modify-write function
    240 * @clkdm_clk_enable: pointer to clockdomain enable function
    241 * @clkdm_clk_disable: pointer to clockdomain disable function
    242 * @clkdm_lookup: pointer to clockdomain lookup function
    243 * @cm_wait_module_ready: pointer to CM module wait ready function
    244 * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
    245 *
    246 * Low-level ops are generally used by the basic clock types (clk-gate,
    247 * clk-mux, clk-divider etc.) to provide support for various low-level
    248 * hadrware interfaces (direct MMIO, regmap etc.), and is initialized
    249 * by board code. Low-level ops also contain some other platform specific
    250 * operations not provided directly by clock drivers.
    251 */
    252struct ti_clk_ll_ops {
    253	u32	(*clk_readl)(const struct clk_omap_reg *reg);
    254	void	(*clk_writel)(u32 val, const struct clk_omap_reg *reg);
    255	void	(*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
    256	int	(*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
    257	int	(*clkdm_clk_disable)(struct clockdomain *clkdm,
    258				     struct clk *clk);
    259	struct clockdomain * (*clkdm_lookup)(const char *name);
    260	int	(*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
    261					u8 idlest_shift);
    262	int	(*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
    263				       s16 *prcm_inst, u8 *idlest_reg_id);
    264};
    265
    266#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
    267
    268bool omap2_clk_is_hw_omap(struct clk_hw *hw);
    269int omap2_clk_disable_autoidle_all(void);
    270int omap2_clk_enable_autoidle_all(void);
    271int omap2_clk_allow_idle(struct clk *clk);
    272int omap2_clk_deny_idle(struct clk *clk);
    273unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
    274				    unsigned long parent_rate);
    275int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
    276			     unsigned long parent_rate);
    277void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
    278void omap2xxx_clkt_vps_init(void);
    279unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
    280
    281void ti_dt_clk_init_retry_clks(void);
    282void ti_dt_clockdomains_setup(void);
    283int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
    284
    285struct regmap;
    286
    287int omap2_clk_provider_init(struct device_node *parent, int index,
    288			    struct regmap *syscon, void __iomem *mem);
    289void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
    290
    291int omap3430_dt_clk_init(void);
    292int omap3630_dt_clk_init(void);
    293int am35xx_dt_clk_init(void);
    294int dm814x_dt_clk_init(void);
    295int dm816x_dt_clk_init(void);
    296int omap4xxx_dt_clk_init(void);
    297int omap5xxx_dt_clk_init(void);
    298int dra7xx_dt_clk_init(void);
    299int am33xx_dt_clk_init(void);
    300int am43xx_dt_clk_init(void);
    301int omap2420_dt_clk_init(void);
    302int omap2430_dt_clk_init(void);
    303
    304struct ti_clk_features {
    305	u32 flags;
    306	long fint_min;
    307	long fint_max;
    308	long fint_band1_max;
    309	long fint_band2_min;
    310	u8 dpll_bypass_vals;
    311	u8 cm_idlest_val;
    312};
    313
    314#define TI_CLK_DPLL_HAS_FREQSEL			BIT(0)
    315#define TI_CLK_DPLL4_DENY_REPROGRAM		BIT(1)
    316#define TI_CLK_DISABLE_CLKDM_CONTROL		BIT(2)
    317#define TI_CLK_ERRATA_I810			BIT(3)
    318#define TI_CLK_CLKCTRL_COMPAT			BIT(4)
    319#define TI_CLK_DEVICE_TYPE_GP			BIT(5)
    320
    321void ti_clk_setup_features(struct ti_clk_features *features);
    322const struct ti_clk_features *ti_clk_get_features(void);
    323bool ti_clk_is_in_standby(struct clk *clk);
    324int omap3_noncore_dpll_save_context(struct clk_hw *hw);
    325void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
    326
    327int omap3_core_dpll_save_context(struct clk_hw *hw);
    328void omap3_core_dpll_restore_context(struct clk_hw *hw);
    329
    330extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
    331
    332#ifdef CONFIG_ATAGS
    333int omap3430_clk_legacy_init(void);
    334int omap3430es1_clk_legacy_init(void);
    335int omap36xx_clk_legacy_init(void);
    336int am35xx_clk_legacy_init(void);
    337#else
    338static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
    339static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
    340static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
    341static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
    342#endif
    343
    344
    345#endif