coresight-pmu.h (1355B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7#ifndef _LINUX_CORESIGHT_PMU_H 8#define _LINUX_CORESIGHT_PMU_H 9 10#define CORESIGHT_ETM_PMU_NAME "cs_etm" 11#define CORESIGHT_ETM_PMU_SEED 0x10 12 13/* 14 * Below are the definition of bit offsets for perf option, and works as 15 * arbitrary values for all ETM versions. 16 * 17 * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, 18 * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and 19 * directly use below macros as config bits. 20 */ 21#define ETM_OPT_CYCACC 12 22#define ETM_OPT_CTXTID 14 23#define ETM_OPT_CTXTID2 15 24#define ETM_OPT_TS 28 25#define ETM_OPT_RETSTK 29 26 27/* ETMv4 CONFIGR programming bits for the ETM OPTs */ 28#define ETM4_CFG_BIT_CYCACC 4 29#define ETM4_CFG_BIT_CTXTID 6 30#define ETM4_CFG_BIT_VMID 7 31#define ETM4_CFG_BIT_TS 11 32#define ETM4_CFG_BIT_RETSTK 12 33#define ETM4_CFG_BIT_VMID_OPT 15 34 35static inline int coresight_get_trace_id(int cpu) 36{ 37 /* 38 * A trace ID of value 0 is invalid, so let's start at some 39 * random value that fits in 7 bits and go from there. Since 40 * the common convention is to have data trace IDs be I(N) + 1, 41 * set instruction trace IDs as a function of the CPU number. 42 */ 43 return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); 44} 45 46#endif