cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

eisa.h (3031B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _LINUX_EISA_H
      3#define _LINUX_EISA_H
      4
      5#include <linux/ioport.h>
      6#include <linux/device.h>
      7#include <linux/mod_devicetable.h>
      8
      9#define EISA_MAX_SLOTS 8
     10
     11#define EISA_MAX_RESOURCES 4
     12
     13/* A few EISA constants/offsets... */
     14
     15#define EISA_DMA1_STATUS            8
     16#define EISA_INT1_CTRL           0x20
     17#define EISA_INT1_MASK           0x21
     18#define EISA_INT2_CTRL           0xA0
     19#define EISA_INT2_MASK           0xA1
     20#define EISA_DMA2_STATUS         0xD0
     21#define EISA_DMA2_WRITE_SINGLE   0xD4
     22#define EISA_EXT_NMI_RESET_CTRL 0x461
     23#define EISA_INT1_EDGE_LEVEL    0x4D0
     24#define EISA_INT2_EDGE_LEVEL    0x4D1
     25#define EISA_VENDOR_ID_OFFSET   0xC80
     26#define EISA_CONFIG_OFFSET      0xC84
     27
     28#define EISA_CONFIG_ENABLED         1
     29#define EISA_CONFIG_FORCED          2
     30
     31/* There is not much we can say about an EISA device, apart from
     32 * signature, slot number, and base address. dma_mask is set by
     33 * default to parent device mask..*/
     34
     35struct eisa_device {
     36	struct eisa_device_id id;
     37	int                   slot;
     38	int                   state;
     39	unsigned long         base_addr;
     40	struct resource       res[EISA_MAX_RESOURCES];
     41	u64                   dma_mask;
     42	struct device         dev; /* generic device */
     43#ifdef CONFIG_EISA_NAMES
     44	char		      pretty_name[50];
     45#endif
     46};
     47
     48#define to_eisa_device(n) container_of(n, struct eisa_device, dev)
     49
     50static inline int eisa_get_region_index (void *addr)
     51{
     52	unsigned long x = (unsigned long) addr;
     53
     54	x &= 0xc00;
     55	return (x >> 12);
     56}
     57
     58struct eisa_driver {
     59	const struct eisa_device_id *id_table;
     60	struct device_driver         driver;
     61};
     62
     63#define to_eisa_driver(drv) container_of(drv,struct eisa_driver, driver)
     64
     65/* These external functions are only available when EISA support is enabled. */
     66#ifdef CONFIG_EISA
     67
     68extern struct bus_type eisa_bus_type;
     69int eisa_driver_register (struct eisa_driver *edrv);
     70void eisa_driver_unregister (struct eisa_driver *edrv);
     71
     72#else /* !CONFIG_EISA */
     73
     74static inline int eisa_driver_register (struct eisa_driver *edrv) { return 0; }
     75static inline void eisa_driver_unregister (struct eisa_driver *edrv) { }
     76
     77#endif /* !CONFIG_EISA */
     78
     79/* Mimics pci.h... */
     80static inline void *eisa_get_drvdata (struct eisa_device *edev)
     81{
     82        return dev_get_drvdata(&edev->dev);
     83}
     84
     85static inline void eisa_set_drvdata (struct eisa_device *edev, void *data)
     86{
     87        dev_set_drvdata(&edev->dev, data);
     88}
     89
     90/* The EISA root device. There's rumours about machines with multiple
     91 * busses (PA-RISC ?), so we try to handle that. */
     92
     93struct eisa_root_device {
     94	struct device   *dev;	 /* Pointer to bridge device */
     95	struct resource *res;
     96	unsigned long    bus_base_addr;
     97	int		 slots;  /* Max slot number */
     98	int		 force_probe; /* Probe even when no slot 0 */
     99	u64		 dma_mask; /* from bridge device */
    100	int              bus_nr; /* Set by eisa_root_register */
    101	struct resource  eisa_root_res;	/* ditto */
    102};
    103
    104int eisa_root_register (struct eisa_root_device *root);
    105
    106#ifdef CONFIG_EISA
    107extern int EISA_bus;
    108#else
    109# define EISA_bus 0
    110#endif
    111
    112#endif