fpga-mgr.h (7562B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * FPGA Framework 4 * 5 * Copyright (C) 2013-2016 Altera Corporation 6 * Copyright (C) 2017 Intel Corporation 7 */ 8#ifndef _LINUX_FPGA_MGR_H 9#define _LINUX_FPGA_MGR_H 10 11#include <linux/mutex.h> 12#include <linux/platform_device.h> 13 14struct fpga_manager; 15struct sg_table; 16 17/** 18 * enum fpga_mgr_states - fpga framework states 19 * @FPGA_MGR_STATE_UNKNOWN: can't determine state 20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off 21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up 22 * @FPGA_MGR_STATE_RESET: FPGA in reset state 23 * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress 24 * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed 25 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming 26 * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage 27 * @FPGA_MGR_STATE_WRITE: writing image to FPGA 28 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA 29 * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps 30 * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE 31 * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating 32 */ 33enum fpga_mgr_states { 34 /* default FPGA states */ 35 FPGA_MGR_STATE_UNKNOWN, 36 FPGA_MGR_STATE_POWER_OFF, 37 FPGA_MGR_STATE_POWER_UP, 38 FPGA_MGR_STATE_RESET, 39 40 /* getting an image for loading */ 41 FPGA_MGR_STATE_FIRMWARE_REQ, 42 FPGA_MGR_STATE_FIRMWARE_REQ_ERR, 43 44 /* write sequence: init, write, complete */ 45 FPGA_MGR_STATE_WRITE_INIT, 46 FPGA_MGR_STATE_WRITE_INIT_ERR, 47 FPGA_MGR_STATE_WRITE, 48 FPGA_MGR_STATE_WRITE_ERR, 49 FPGA_MGR_STATE_WRITE_COMPLETE, 50 FPGA_MGR_STATE_WRITE_COMPLETE_ERR, 51 52 /* fpga is programmed and operating */ 53 FPGA_MGR_STATE_OPERATING, 54}; 55 56/** 57 * DOC: FPGA Manager flags 58 * 59 * Flags used in the &fpga_image_info->flags field 60 * 61 * %FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported 62 * 63 * %FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting 64 * 65 * %FPGA_MGR_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted 66 * 67 * %FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first 68 * 69 * %FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed 70 */ 71#define FPGA_MGR_PARTIAL_RECONFIG BIT(0) 72#define FPGA_MGR_EXTERNAL_CONFIG BIT(1) 73#define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) 74#define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) 75#define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) 76 77/** 78 * struct fpga_image_info - information specific to an FPGA image 79 * @flags: boolean flags as defined above 80 * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) 81 * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) 82 * @config_complete_timeout_us: maximum time for FPGA to switch to operating 83 * status in the write_complete op. 84 * @firmware_name: name of FPGA image firmware file 85 * @sgt: scatter/gather table containing FPGA image 86 * @buf: contiguous buffer containing FPGA image 87 * @count: size of buf 88 * @region_id: id of target region 89 * @dev: device that owns this 90 * @overlay: Device Tree overlay 91 */ 92struct fpga_image_info { 93 u32 flags; 94 u32 enable_timeout_us; 95 u32 disable_timeout_us; 96 u32 config_complete_timeout_us; 97 char *firmware_name; 98 struct sg_table *sgt; 99 const char *buf; 100 size_t count; 101 int region_id; 102 struct device *dev; 103#ifdef CONFIG_OF 104 struct device_node *overlay; 105#endif 106}; 107 108/** 109 * struct fpga_compat_id - id for compatibility check 110 * 111 * @id_h: high 64bit of the compat_id 112 * @id_l: low 64bit of the compat_id 113 */ 114struct fpga_compat_id { 115 u64 id_h; 116 u64 id_l; 117}; 118 119/** 120 * struct fpga_manager_info - collection of parameters for an FPGA Manager 121 * @name: fpga manager name 122 * @compat_id: FPGA manager id for compatibility check. 123 * @mops: pointer to structure of fpga manager ops 124 * @priv: fpga manager private data 125 * 126 * fpga_manager_info contains parameters for the register_full function. 127 * These are separated into an info structure because they some are optional 128 * others could be added to in the future. The info structure facilitates 129 * maintaining a stable API. 130 */ 131struct fpga_manager_info { 132 const char *name; 133 struct fpga_compat_id *compat_id; 134 const struct fpga_manager_ops *mops; 135 void *priv; 136}; 137 138/** 139 * struct fpga_manager_ops - ops for low level fpga manager drivers 140 * @initial_header_size: Maximum number of bytes that should be passed into write_init 141 * @state: returns an enum value of the FPGA's state 142 * @status: returns status of the FPGA, including reconfiguration error code 143 * @write_init: prepare the FPGA to receive configuration data 144 * @write: write count bytes of configuration data to the FPGA 145 * @write_sg: write the scatter list of configuration data to the FPGA 146 * @write_complete: set FPGA to operating state after writing is done 147 * @fpga_remove: optional: Set FPGA into a specific state during driver remove 148 * @groups: optional attribute groups. 149 * 150 * fpga_manager_ops are the low level functions implemented by a specific 151 * fpga manager driver. The optional ones are tested for NULL before being 152 * called, so leaving them out is fine. 153 */ 154struct fpga_manager_ops { 155 size_t initial_header_size; 156 enum fpga_mgr_states (*state)(struct fpga_manager *mgr); 157 u64 (*status)(struct fpga_manager *mgr); 158 int (*write_init)(struct fpga_manager *mgr, 159 struct fpga_image_info *info, 160 const char *buf, size_t count); 161 int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); 162 int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); 163 int (*write_complete)(struct fpga_manager *mgr, 164 struct fpga_image_info *info); 165 void (*fpga_remove)(struct fpga_manager *mgr); 166 const struct attribute_group **groups; 167}; 168 169/* FPGA manager status: Partial/Full Reconfiguration errors */ 170#define FPGA_MGR_STATUS_OPERATION_ERR BIT(0) 171#define FPGA_MGR_STATUS_CRC_ERR BIT(1) 172#define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR BIT(2) 173#define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3) 174#define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4) 175 176/** 177 * struct fpga_manager - fpga manager structure 178 * @name: name of low level fpga manager 179 * @dev: fpga manager device 180 * @ref_mutex: only allows one reference to fpga manager 181 * @state: state of fpga manager 182 * @compat_id: FPGA manager id for compatibility check. 183 * @mops: pointer to struct of fpga manager ops 184 * @priv: low level driver private date 185 */ 186struct fpga_manager { 187 const char *name; 188 struct device dev; 189 struct mutex ref_mutex; 190 enum fpga_mgr_states state; 191 struct fpga_compat_id *compat_id; 192 const struct fpga_manager_ops *mops; 193 void *priv; 194}; 195 196#define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) 197 198struct fpga_image_info *fpga_image_info_alloc(struct device *dev); 199 200void fpga_image_info_free(struct fpga_image_info *info); 201 202int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info); 203 204int fpga_mgr_lock(struct fpga_manager *mgr); 205void fpga_mgr_unlock(struct fpga_manager *mgr); 206 207struct fpga_manager *of_fpga_mgr_get(struct device_node *node); 208 209struct fpga_manager *fpga_mgr_get(struct device *dev); 210 211void fpga_mgr_put(struct fpga_manager *mgr); 212 213struct fpga_manager * 214fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info); 215 216struct fpga_manager * 217fpga_mgr_register(struct device *parent, const char *name, 218 const struct fpga_manager_ops *mops, void *priv); 219void fpga_mgr_unregister(struct fpga_manager *mgr); 220 221struct fpga_manager * 222devm_fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info); 223struct fpga_manager * 224devm_fpga_mgr_register(struct device *parent, const char *name, 225 const struct fpga_manager_ops *mops, void *priv); 226 227#endif /*_LINUX_FPGA_MGR_H */