enetc_mdio.h (1596B)
1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2/* Copyright 2019 NXP */ 3 4#ifndef _FSL_ENETC_MDIO_H_ 5#define _FSL_ENETC_MDIO_H_ 6 7#include <linux/phy.h> 8 9/* PCS registers */ 10#define ENETC_PCS_LINK_TIMER1 0x12 11#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0 12#define ENETC_PCS_LINK_TIMER2 0x13 13#define ENETC_PCS_LINK_TIMER2_VAL 0x0003 14#define ENETC_PCS_IF_MODE 0x14 15#define ENETC_PCS_IF_MODE_SGMII_EN BIT(0) 16#define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1) 17#define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2)) 18#define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3) 19 20/* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset 21 * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS 22 * still thinks it's at gigabit. 23 */ 24enum enetc_pcs_speed { 25 ENETC_PCS_SPEED_10 = 0, 26 ENETC_PCS_SPEED_100 = 1, 27 ENETC_PCS_SPEED_1000 = 2, 28 ENETC_PCS_SPEED_2500 = 2, 29}; 30 31struct enetc_hw; 32 33struct enetc_mdio_priv { 34 struct enetc_hw *hw; 35 int mdio_base; 36}; 37 38#if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO) 39 40int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum); 41int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value); 42struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs); 43 44#else 45 46static inline int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum) 47{ return -EINVAL; } 48static inline int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, 49 u16 value) 50{ return -EINVAL; } 51struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) 52{ return ERR_PTR(-EINVAL); } 53 54#endif 55 56#endif