cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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stm32-timer-trigger.h (1919B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) STMicroelectronics 2016
      4 *
      5 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
      6 */
      7
      8#ifndef _STM32_TIMER_TRIGGER_H_
      9#define _STM32_TIMER_TRIGGER_H_
     10
     11#define TIM1_TRGO	"tim1_trgo"
     12#define TIM1_TRGO2	"tim1_trgo2"
     13#define TIM1_CH1	"tim1_ch1"
     14#define TIM1_CH2	"tim1_ch2"
     15#define TIM1_CH3	"tim1_ch3"
     16#define TIM1_CH4	"tim1_ch4"
     17
     18#define TIM2_TRGO	"tim2_trgo"
     19#define TIM2_CH1	"tim2_ch1"
     20#define TIM2_CH2	"tim2_ch2"
     21#define TIM2_CH3	"tim2_ch3"
     22#define TIM2_CH4	"tim2_ch4"
     23
     24#define TIM3_TRGO	"tim3_trgo"
     25#define TIM3_CH1	"tim3_ch1"
     26#define TIM3_CH2	"tim3_ch2"
     27#define TIM3_CH3	"tim3_ch3"
     28#define TIM3_CH4	"tim3_ch4"
     29
     30#define TIM4_TRGO	"tim4_trgo"
     31#define TIM4_CH1	"tim4_ch1"
     32#define TIM4_CH2	"tim4_ch2"
     33#define TIM4_CH3	"tim4_ch3"
     34#define TIM4_CH4	"tim4_ch4"
     35
     36#define TIM5_TRGO	"tim5_trgo"
     37#define TIM5_CH1	"tim5_ch1"
     38#define TIM5_CH2	"tim5_ch2"
     39#define TIM5_CH3	"tim5_ch3"
     40#define TIM5_CH4	"tim5_ch4"
     41
     42#define TIM6_TRGO	"tim6_trgo"
     43
     44#define TIM7_TRGO	"tim7_trgo"
     45
     46#define TIM8_TRGO	"tim8_trgo"
     47#define TIM8_TRGO2	"tim8_trgo2"
     48#define TIM8_CH1	"tim8_ch1"
     49#define TIM8_CH2	"tim8_ch2"
     50#define TIM8_CH3	"tim8_ch3"
     51#define TIM8_CH4	"tim8_ch4"
     52
     53#define TIM9_TRGO	"tim9_trgo"
     54#define TIM9_CH1	"tim9_ch1"
     55#define TIM9_CH2	"tim9_ch2"
     56
     57#define TIM10_OC1	"tim10_oc1"
     58
     59#define TIM11_OC1	"tim11_oc1"
     60
     61#define TIM12_TRGO	"tim12_trgo"
     62#define TIM12_CH1	"tim12_ch1"
     63#define TIM12_CH2	"tim12_ch2"
     64
     65#define TIM13_OC1	"tim13_oc1"
     66
     67#define TIM14_OC1	"tim14_oc1"
     68
     69#define TIM15_TRGO	"tim15_trgo"
     70
     71#define TIM16_OC1	"tim16_oc1"
     72
     73#define TIM17_OC1	"tim17_oc1"
     74
     75#if IS_REACHABLE(CONFIG_IIO_STM32_TIMER_TRIGGER)
     76bool is_stm32_timer_trigger(struct iio_trigger *trig);
     77#else
     78static inline bool is_stm32_timer_trigger(struct iio_trigger *trig)
     79{
     80#if IS_ENABLED(CONFIG_IIO_STM32_TIMER_TRIGGER)
     81	pr_warn_once("stm32-timer-trigger not linked in\n");
     82#endif
     83	return false;
     84}
     85#endif
     86#endif