cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq-bcm2836.h (1935B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
      4 *
      5 * Copyright 2015 Broadcom
      6 */
      7
      8#define LOCAL_CONTROL			0x000
      9#define LOCAL_PRESCALER			0x008
     10
     11/*
     12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
     13 * next 2 bits identify the CPU that the GPU FIQ goes to.
     14 */
     15#define LOCAL_GPU_ROUTING		0x00c
     16/* When setting bits 0-3, enables PMU interrupts on that CPU. */
     17#define LOCAL_PM_ROUTING_SET		0x010
     18/* When setting bits 0-3, disables PMU interrupts on that CPU. */
     19#define LOCAL_PM_ROUTING_CLR		0x014
     20/*
     21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
     22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
     23 * bits).
     24 */
     25#define LOCAL_TIMER_INT_CONTROL0	0x040
     26/*
     27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
     28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
     29 * override the IRQ bits).
     30 */
     31#define LOCAL_MAILBOX_INT_CONTROL0	0x050
     32/*
     33 * The CPU's interrupt status register.  Bits are defined by the
     34 * LOCAL_IRQ_* bits below.
     35 */
     36#define LOCAL_IRQ_PENDING0		0x060
     37/* Same status bits as above, but for FIQ. */
     38#define LOCAL_FIQ_PENDING0		0x070
     39/*
     40 * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
     41 * these bits are organized by mailbox number and then CPU number.  We
     42 * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
     43 * any bit is set.
     44 */
     45#define LOCAL_MAILBOX0_SET0		0x080
     46#define LOCAL_MAILBOX3_SET0		0x08c
     47/* Mailbox write-to-clear bits. */
     48#define LOCAL_MAILBOX0_CLR0		0x0c0
     49#define LOCAL_MAILBOX3_CLR0		0x0cc
     50
     51#define LOCAL_IRQ_CNTPSIRQ	0
     52#define LOCAL_IRQ_CNTPNSIRQ	1
     53#define LOCAL_IRQ_CNTHPIRQ	2
     54#define LOCAL_IRQ_CNTVIRQ	3
     55#define LOCAL_IRQ_MAILBOX0	4
     56#define LOCAL_IRQ_MAILBOX1	5
     57#define LOCAL_IRQ_MAILBOX2	6
     58#define LOCAL_IRQ_MAILBOX3	7
     59#define LOCAL_IRQ_GPU_FAST	8
     60#define LOCAL_IRQ_PMU_FAST	9
     61#define LAST_IRQ		LOCAL_IRQ_PMU_FAST