mdio-xgene.h (3598B)
1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* Applied Micro X-Gene SoC MDIO Driver 3 * 4 * Copyright (c) 2016, Applied Micro Circuits Corporation 5 * Author: Iyappan Subramanian <isubramanian@apm.com> 6 */ 7 8#ifndef __MDIO_XGENE_H__ 9#define __MDIO_XGENE_H__ 10 11#define BLOCK_XG_MDIO_CSR_OFFSET 0x5000 12#define BLOCK_DIAG_CSR_OFFSET 0xd000 13#define XGENET_CONFIG_REG_ADDR 0x20 14 15#define MAC_ADDR_REG_OFFSET 0x00 16#define MAC_COMMAND_REG_OFFSET 0x04 17#define MAC_WRITE_REG_OFFSET 0x08 18#define MAC_READ_REG_OFFSET 0x0c 19#define MAC_COMMAND_DONE_REG_OFFSET 0x10 20 21#define CLKEN_OFFSET 0x08 22#define SRST_OFFSET 0x00 23 24#define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70 25#define MENET_BLOCK_MEM_RDY_ADDR 0x74 26 27#define MAC_CONFIG_1_ADDR 0x00 28#define MII_MGMT_COMMAND_ADDR 0x24 29#define MII_MGMT_ADDRESS_ADDR 0x28 30#define MII_MGMT_CONTROL_ADDR 0x2c 31#define MII_MGMT_STATUS_ADDR 0x30 32#define MII_MGMT_INDICATORS_ADDR 0x34 33#define SOFT_RESET BIT(31) 34 35#define MII_MGMT_CONFIG_ADDR 0x20 36#define MII_MGMT_COMMAND_ADDR 0x24 37#define MII_MGMT_ADDRESS_ADDR 0x28 38#define MII_MGMT_CONTROL_ADDR 0x2c 39#define MII_MGMT_STATUS_ADDR 0x30 40#define MII_MGMT_INDICATORS_ADDR 0x34 41 42#define MIIM_COMMAND_ADDR 0x20 43#define MIIM_FIELD_ADDR 0x24 44#define MIIM_CONFIGURATION_ADDR 0x28 45#define MIIM_LINKFAILVECTOR_ADDR 0x2c 46#define MIIM_INDICATOR_ADDR 0x30 47#define MIIMRD_FIELD_ADDR 0x34 48 49#define MDIO_CSR_OFFSET 0x5000 50 51#define REG_ADDR_POS 0 52#define REG_ADDR_LEN 5 53#define PHY_ADDR_POS 8 54#define PHY_ADDR_LEN 5 55 56#define HSTMIIMWRDAT_POS 0 57#define HSTMIIMWRDAT_LEN 16 58#define HSTPHYADX_POS 23 59#define HSTPHYADX_LEN 5 60#define HSTREGADX_POS 18 61#define HSTREGADX_LEN 5 62#define HSTLDCMD BIT(3) 63#define HSTMIIMCMD_POS 0 64#define HSTMIIMCMD_LEN 3 65 66#define BUSY_MASK BIT(0) 67#define READ_CYCLE_MASK BIT(0) 68 69enum xgene_enet_cmd { 70 XGENE_ENET_WR_CMD = BIT(31), 71 XGENE_ENET_RD_CMD = BIT(30) 72}; 73 74enum { 75 MIIM_CMD_IDLE, 76 MIIM_CMD_LEGACY_WRITE, 77 MIIM_CMD_LEGACY_READ, 78}; 79 80enum xgene_mdio_id { 81 XGENE_MDIO_RGMII = 1, 82 XGENE_MDIO_XFI 83}; 84 85struct xgene_mdio_pdata { 86 struct clk *clk; 87 struct device *dev; 88 void __iomem *mac_csr_addr; 89 void __iomem *diag_csr_addr; 90 void __iomem *mdio_csr_addr; 91 struct mii_bus *mdio_bus; 92 int mdio_id; 93 spinlock_t mac_lock; /* mac lock */ 94}; 95 96/* Set the specified value into a bit-field defined by its starting position 97 * and length within a single u64. 98 */ 99static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val) 100{ 101 return (val & ((1ULL << len) - 1)) << pos; 102} 103 104#define SET_VAL(field, val) \ 105 xgene_enet_set_field_value(field ## _POS, field ## _LEN, val) 106 107#define SET_BIT(field) \ 108 xgene_enet_set_field_value(field ## _POS, 1, 1) 109 110/* Get the value from a bit-field defined by its starting position 111 * and length within the specified u64. 112 */ 113static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src) 114{ 115 return (src >> pos) & ((1ULL << len) - 1); 116} 117 118#define GET_VAL(field, src) \ 119 xgene_enet_get_field_value(field ## _POS, field ## _LEN, src) 120 121#define GET_BIT(field, src) \ 122 xgene_enet_get_field_value(field ## _POS, 1, src) 123 124u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr); 125void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data); 126int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg); 127int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data); 128struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr); 129 130#endif /* __MDIO_XGENE_H__ */