cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dm355evm_msp.h (2879B)


      1/*
      2 * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board
      3 */
      4#ifndef __LINUX_I2C_DM355EVM_MSP
      5#define __LINUX_I2C_DM355EVM_MSP
      6
      7/*
      8 * Written against Spectrum's writeup for the A4 firmware revision,
      9 * and tweaked to match source and rev D2 schematics by removing CPLD
     10 * and NOR flash hooks (which were last appropriate in rev B boards).
     11 *
     12 * Note that the firmware supports a flavor of write posting ... to be
     13 * sure a write completes, issue another read or write.
     14 */
     15
     16/* utilities to access "registers" emulated by msp430 firmware */
     17extern int dm355evm_msp_write(u8 value, u8 reg);
     18extern int dm355evm_msp_read(u8 reg);
     19
     20
     21/* command/control registers */
     22#define DM355EVM_MSP_COMMAND		0x00
     23#	define MSP_COMMAND_NULL		0
     24#	define MSP_COMMAND_RESET_COLD	1
     25#	define MSP_COMMAND_RESET_WARM	2
     26#	define MSP_COMMAND_RESET_WARM_I	3
     27#	define MSP_COMMAND_POWEROFF	4
     28#	define MSP_COMMAND_IR_REINIT	5
     29#define DM355EVM_MSP_STATUS		0x01
     30#	define MSP_STATUS_BAD_OFFSET	BIT(0)
     31#	define MSP_STATUS_BAD_COMMAND	BIT(1)
     32#	define MSP_STATUS_POWER_ERROR	BIT(2)
     33#	define MSP_STATUS_RXBUF_OVERRUN	BIT(3)
     34#define DM355EVM_MSP_RESET		0x02	/* 0 bits == in reset */
     35#	define MSP_RESET_DC5		BIT(0)
     36#	define MSP_RESET_TVP5154	BIT(2)
     37#	define MSP_RESET_IMAGER		BIT(3)
     38#	define MSP_RESET_ETHERNET	BIT(4)
     39#	define MSP_RESET_SYS		BIT(5)
     40#	define MSP_RESET_AIC33		BIT(7)
     41
     42/* GPIO registers ... bit patterns mostly match the source MSP ports */
     43#define DM355EVM_MSP_LED		0x03	/* active low (MSP P4) */
     44#define DM355EVM_MSP_SWITCH1		0x04	/* (MSP P5, masked) */
     45#	define MSP_SWITCH1_SW6_1	BIT(0)
     46#	define MSP_SWITCH1_SW6_2	BIT(1)
     47#	define MSP_SWITCH1_SW6_3	BIT(2)
     48#	define MSP_SWITCH1_SW6_4	BIT(3)
     49#	define MSP_SWITCH1_J1		BIT(4)	/* NTSC/PAL */
     50#	define MSP_SWITCH1_MSP_INT	BIT(5)	/* active low */
     51#define DM355EVM_MSP_SWITCH2		0x05	/* (MSP P6, masked) */
     52#	define MSP_SWITCH2_SW10		BIT(3)
     53#	define MSP_SWITCH2_SW11		BIT(4)
     54#	define MSP_SWITCH2_SW12		BIT(5)
     55#	define MSP_SWITCH2_SW13		BIT(6)
     56#	define MSP_SWITCH2_SW14		BIT(7)
     57#define DM355EVM_MSP_SDMMC		0x06	/* (MSP P2, masked) */
     58#	define MSP_SDMMC_0_WP		BIT(1)
     59#	define MSP_SDMMC_0_CD		BIT(2)	/* active low */
     60#	define MSP_SDMMC_1_WP		BIT(3)
     61#	define MSP_SDMMC_1_CD		BIT(4)	/* active low */
     62#define DM355EVM_MSP_FIRMREV		0x07	/* not a GPIO (out of order) */
     63#define DM355EVM_MSP_VIDEO_IN		0x08	/* (MSP P3, masked) */
     64#	define MSP_VIDEO_IMAGER		BIT(7)	/* low == tvp5146 */
     65
     66/* power supply registers are currently omitted */
     67
     68/* RTC registers */
     69#define DM355EVM_MSP_RTC_0		0x12	/* LSB */
     70#define DM355EVM_MSP_RTC_1		0x13
     71#define DM355EVM_MSP_RTC_2		0x14
     72#define DM355EVM_MSP_RTC_3		0x15	/* MSB */
     73
     74/* input event queue registers; code == ((HIGH << 8) | LOW) */
     75#define DM355EVM_MSP_INPUT_COUNT	0x16	/* decrement by reading LOW */
     76#define DM355EVM_MSP_INPUT_HIGH		0x17
     77#define DM355EVM_MSP_INPUT_LOW		0x18
     78
     79#endif /* __LINUX_I2C_DM355EVM_MSP */