intel-m10-bmc.h (4907B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Intel MAX 10 Board Management Controller chip. 4 * 5 * Copyright (C) 2018-2020 Intel Corporation, Inc. 6 */ 7#ifndef __MFD_INTEL_M10_BMC_H 8#define __MFD_INTEL_M10_BMC_H 9 10#include <linux/regmap.h> 11 12#define M10BMC_LEGACY_BUILD_VER 0x300468 13#define M10BMC_SYS_BASE 0x300800 14#define M10BMC_SYS_END 0x300fff 15#define M10BMC_FLASH_BASE 0x10000000 16#define M10BMC_FLASH_END 0x1fffffff 17#define M10BMC_MEM_END M10BMC_FLASH_END 18 19#define M10BMC_STAGING_BASE 0x18000000 20#define M10BMC_STAGING_SIZE 0x3800000 21 22/* Register offset of system registers */ 23#define NIOS2_FW_VERSION 0x0 24#define M10BMC_MAC_LOW 0x10 25#define M10BMC_MAC_BYTE4 GENMASK(7, 0) 26#define M10BMC_MAC_BYTE3 GENMASK(15, 8) 27#define M10BMC_MAC_BYTE2 GENMASK(23, 16) 28#define M10BMC_MAC_BYTE1 GENMASK(31, 24) 29#define M10BMC_MAC_HIGH 0x14 30#define M10BMC_MAC_BYTE6 GENMASK(7, 0) 31#define M10BMC_MAC_BYTE5 GENMASK(15, 8) 32#define M10BMC_MAC_COUNT GENMASK(23, 16) 33#define M10BMC_TEST_REG 0x3c 34#define M10BMC_BUILD_VER 0x68 35#define M10BMC_VER_MAJOR_MSK GENMASK(23, 16) 36#define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24) 37#define M10BMC_VER_LEGACY_INVALID 0xffffffff 38 39/* Secure update doorbell register, in system register region */ 40#define M10BMC_DOORBELL 0x400 41 42/* Authorization Result register, in system register region */ 43#define M10BMC_AUTH_RESULT 0x404 44 45/* Doorbell register fields */ 46#define DRBL_RSU_REQUEST BIT(0) 47#define DRBL_RSU_PROGRESS GENMASK(7, 4) 48#define DRBL_HOST_STATUS GENMASK(11, 8) 49#define DRBL_RSU_STATUS GENMASK(23, 16) 50#define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24) 51#define DRBL_PKVL1_POLL_EN BIT(25) 52#define DRBL_PKVL2_POLL_EN BIT(26) 53#define DRBL_CONFIG_SEL BIT(28) 54#define DRBL_REBOOT_REQ BIT(29) 55#define DRBL_REBOOT_DISABLED BIT(30) 56 57/* Progress states */ 58#define RSU_PROG_IDLE 0x0 59#define RSU_PROG_PREPARE 0x1 60#define RSU_PROG_READY 0x3 61#define RSU_PROG_AUTHENTICATING 0x4 62#define RSU_PROG_COPYING 0x5 63#define RSU_PROG_UPDATE_CANCEL 0x6 64#define RSU_PROG_PROGRAM_KEY_HASH 0x7 65#define RSU_PROG_RSU_DONE 0x8 66#define RSU_PROG_PKVL_PROM_DONE 0x9 67 68/* Device and error states */ 69#define RSU_STAT_NORMAL 0x0 70#define RSU_STAT_TIMEOUT 0x1 71#define RSU_STAT_AUTH_FAIL 0x2 72#define RSU_STAT_COPY_FAIL 0x3 73#define RSU_STAT_FATAL 0x4 74#define RSU_STAT_PKVL_REJECT 0x5 75#define RSU_STAT_NON_INC 0x6 76#define RSU_STAT_ERASE_FAIL 0x7 77#define RSU_STAT_WEAROUT 0x8 78#define RSU_STAT_NIOS_OK 0x80 79#define RSU_STAT_USER_OK 0x81 80#define RSU_STAT_FACTORY_OK 0x82 81#define RSU_STAT_USER_FAIL 0x83 82#define RSU_STAT_FACTORY_FAIL 0x84 83#define RSU_STAT_NIOS_FLASH_ERR 0x85 84#define RSU_STAT_FPGA_FLASH_ERR 0x86 85 86#define HOST_STATUS_IDLE 0x0 87#define HOST_STATUS_WRITE_DONE 0x1 88#define HOST_STATUS_ABORT_RSU 0x2 89 90#define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell) 91#define rsu_stat(doorbell) FIELD_GET(DRBL_RSU_STATUS, doorbell) 92 93/* interval 100ms and timeout 5s */ 94#define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000) 95#define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000) 96 97/* RSU PREP Timeout (2 minutes) to erase flash staging area */ 98#define RSU_PREP_INTERVAL_MS 100 99#define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000) 100 101/* RSU Complete Timeout (40 minutes) for full flash update */ 102#define RSU_COMPLETE_INTERVAL_MS 1000 103#define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000) 104 105/* Addresses for security related data in FLASH */ 106#define BMC_REH_ADDR 0x17ffc004 107#define BMC_PROG_ADDR 0x17ffc000 108#define BMC_PROG_MAGIC 0x5746 109 110#define SR_REH_ADDR 0x17ffd004 111#define SR_PROG_ADDR 0x17ffd000 112#define SR_PROG_MAGIC 0x5253 113 114#define PR_REH_ADDR 0x17ffe004 115#define PR_PROG_ADDR 0x17ffe000 116#define PR_PROG_MAGIC 0x5250 117 118/* Address of 4KB inverted bit vector containing staging area FLASH count */ 119#define STAGING_FLASH_COUNT 0x17ffb000 120 121/** 122 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure 123 * @dev: this device 124 * @regmap: the regmap used to access registers by m10bmc itself 125 */ 126struct intel_m10bmc { 127 struct device *dev; 128 struct regmap *regmap; 129}; 130 131/* 132 * register access helper functions. 133 * 134 * m10bmc_raw_read - read m10bmc register per addr 135 * m10bmc_sys_read - read m10bmc system register per offset 136 */ 137static inline int 138m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr, 139 unsigned int *val) 140{ 141 int ret; 142 143 ret = regmap_read(m10bmc->regmap, addr, val); 144 if (ret) 145 dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n", 146 addr, ret); 147 148 return ret; 149} 150 151/* 152 * The base of the system registers could be configured by HW developers, and 153 * in HW SPEC, the base is not added to the addresses of the system registers. 154 * 155 * This macro helps to simplify the accessing of the system registers. And if 156 * the base is reconfigured in HW, SW developers could simply change the 157 * M10BMC_SYS_BASE accordingly. 158 */ 159#define m10bmc_sys_read(m10bmc, offset, val) \ 160 m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val) 161 162#endif /* __MFD_INTEL_M10_BMC_H */