intel_pmc_bxt.h (1542B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef MFD_INTEL_PMC_BXT_H 3#define MFD_INTEL_PMC_BXT_H 4 5/* GCR reg offsets from GCR base */ 6#define PMC_GCR_PMC_CFG_REG 0x08 7#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78 8#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80 9 10/* PMC_CFG_REG bit masks */ 11#define PMC_CFG_NO_REBOOT_EN BIT(4) 12 13/** 14 * struct intel_pmc_dev - Intel PMC device structure 15 * @dev: Pointer to the parent PMC device 16 * @scu: Pointer to the SCU IPC device data structure 17 * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers) 18 * @gcr_lock: Lock used to serialize access to GCR registers 19 * @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not 20 * available 21 */ 22struct intel_pmc_dev { 23 struct device *dev; 24 struct intel_scu_ipc_dev *scu; 25 void __iomem *gcr_mem_base; 26 spinlock_t gcr_lock; 27 struct resource *telem_base; 28}; 29 30#if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT) 31int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data); 32int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val); 33int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data); 34#else 35static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, 36 u64 *data) 37{ 38 return -ENOTSUPP; 39} 40 41static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, 42 u32 mask, u32 val) 43{ 44 return -ENOTSUPP; 45} 46 47static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data) 48{ 49 return -ENOTSUPP; 50} 51#endif 52 53#endif /* MFD_INTEL_PMC_BXT_H */