cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_soc_pmic_mrfld.h (2288B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Header file for Intel Merrifield Basin Cove PMIC
      4 *
      5 * Copyright (C) 2019 Intel Corporation. All rights reserved.
      6 */
      7
      8#ifndef __INTEL_SOC_PMIC_MRFLD_H__
      9#define __INTEL_SOC_PMIC_MRFLD_H__
     10
     11#include <linux/bits.h>
     12
     13#define BCOVE_ID		0x00
     14
     15#define BCOVE_ID_MINREV0	GENMASK(2, 0)
     16#define BCOVE_ID_MAJREV0	GENMASK(5, 3)
     17#define BCOVE_ID_VENDID0	GENMASK(7, 6)
     18
     19#define BCOVE_MINOR(x)		(unsigned int)(((x) & BCOVE_ID_MINREV0) >> 0)
     20#define BCOVE_MAJOR(x)		(unsigned int)(((x) & BCOVE_ID_MAJREV0) >> 3)
     21#define BCOVE_VENDOR(x)		(unsigned int)(((x) & BCOVE_ID_VENDID0) >> 6)
     22
     23#define BCOVE_IRQLVL1		0x01
     24
     25#define BCOVE_PBIRQ		0x02
     26#define BCOVE_TMUIRQ		0x03
     27#define BCOVE_THRMIRQ		0x04
     28#define BCOVE_BCUIRQ		0x05
     29#define BCOVE_ADCIRQ		0x06
     30#define BCOVE_CHGRIRQ0		0x07
     31#define BCOVE_CHGRIRQ1		0x08
     32#define BCOVE_GPIOIRQ		0x09
     33#define BCOVE_CRITIRQ		0x0B
     34
     35#define BCOVE_MIRQLVL1		0x0C
     36
     37#define BCOVE_MPBIRQ		0x0D
     38#define BCOVE_MTMUIRQ		0x0E
     39#define BCOVE_MTHRMIRQ		0x0F
     40#define BCOVE_MBCUIRQ		0x10
     41#define BCOVE_MADCIRQ		0x11
     42#define BCOVE_MCHGRIRQ0		0x12
     43#define BCOVE_MCHGRIRQ1		0x13
     44#define BCOVE_MGPIOIRQ		0x14
     45#define BCOVE_MCRITIRQ		0x16
     46
     47#define BCOVE_SCHGRIRQ0		0x4E
     48#define BCOVE_SCHGRIRQ1		0x4F
     49
     50/* Level 1 IRQs */
     51#define BCOVE_LVL1_PWRBTN	BIT(0)	/* power button */
     52#define BCOVE_LVL1_TMU		BIT(1)	/* time management unit */
     53#define BCOVE_LVL1_THRM		BIT(2)	/* thermal */
     54#define BCOVE_LVL1_BCU		BIT(3)	/* burst control unit */
     55#define BCOVE_LVL1_ADC		BIT(4)	/* ADC */
     56#define BCOVE_LVL1_CHGR		BIT(5)	/* charger */
     57#define BCOVE_LVL1_GPIO		BIT(6)	/* GPIO */
     58#define BCOVE_LVL1_CRIT		BIT(7)	/* critical event */
     59
     60/* Level 2 IRQs: power button */
     61#define BCOVE_PBIRQ_PBTN	BIT(0)
     62#define BCOVE_PBIRQ_UBTN	BIT(1)
     63
     64/* Level 2 IRQs: ADC */
     65#define BCOVE_ADCIRQ_BATTEMP	BIT(2)
     66#define BCOVE_ADCIRQ_SYSTEMP	BIT(3)
     67#define BCOVE_ADCIRQ_BATTID	BIT(4)
     68#define BCOVE_ADCIRQ_VIBATT	BIT(5)
     69#define BCOVE_ADCIRQ_CCTICK	BIT(7)
     70
     71/* Level 2 IRQs: charger */
     72#define BCOVE_CHGRIRQ_BAT0ALRT	BIT(4)
     73#define BCOVE_CHGRIRQ_BAT1ALRT	BIT(5)
     74#define BCOVE_CHGRIRQ_BATCRIT	BIT(6)
     75
     76#define BCOVE_CHGRIRQ_VBUSDET	BIT(0)
     77#define BCOVE_CHGRIRQ_DCDET	BIT(1)
     78#define BCOVE_CHGRIRQ_BATTDET	BIT(2)
     79#define BCOVE_CHGRIRQ_USBIDDET	BIT(3)
     80
     81#endif	/* __INTEL_SOC_PMIC_MRFLD_H__ */