cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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core.h (4013B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (c) 2020 MediaTek Inc.
      4 */
      5
      6#ifndef __MFD_MT6358_CORE_H__
      7#define __MFD_MT6358_CORE_H__
      8
      9struct irq_top_t {
     10	int hwirq_base;
     11	unsigned int num_int_regs;
     12	unsigned int en_reg;
     13	unsigned int en_reg_shift;
     14	unsigned int sta_reg;
     15	unsigned int sta_reg_shift;
     16	unsigned int top_offset;
     17};
     18
     19struct pmic_irq_data {
     20	unsigned int num_top;
     21	unsigned int num_pmic_irqs;
     22	unsigned short top_int_status_reg;
     23	bool *enable_hwirq;
     24	bool *cache_hwirq;
     25	const struct irq_top_t *pmic_ints;
     26};
     27
     28enum mt6358_irq_top_status_shift {
     29	MT6358_BUCK_TOP = 0,
     30	MT6358_LDO_TOP,
     31	MT6358_PSC_TOP,
     32	MT6358_SCK_TOP,
     33	MT6358_BM_TOP,
     34	MT6358_HK_TOP,
     35	MT6358_AUD_TOP,
     36	MT6358_MISC_TOP,
     37};
     38
     39enum mt6358_irq_numbers {
     40	MT6358_IRQ_VPROC11_OC = 0,
     41	MT6358_IRQ_VPROC12_OC,
     42	MT6358_IRQ_VCORE_OC,
     43	MT6358_IRQ_VGPU_OC,
     44	MT6358_IRQ_VMODEM_OC,
     45	MT6358_IRQ_VDRAM1_OC,
     46	MT6358_IRQ_VS1_OC,
     47	MT6358_IRQ_VS2_OC,
     48	MT6358_IRQ_VPA_OC,
     49	MT6358_IRQ_VCORE_PREOC,
     50	MT6358_IRQ_VFE28_OC = 16,
     51	MT6358_IRQ_VXO22_OC,
     52	MT6358_IRQ_VRF18_OC,
     53	MT6358_IRQ_VRF12_OC,
     54	MT6358_IRQ_VEFUSE_OC,
     55	MT6358_IRQ_VCN33_OC,
     56	MT6358_IRQ_VCN28_OC,
     57	MT6358_IRQ_VCN18_OC,
     58	MT6358_IRQ_VCAMA1_OC,
     59	MT6358_IRQ_VCAMA2_OC,
     60	MT6358_IRQ_VCAMD_OC,
     61	MT6358_IRQ_VCAMIO_OC,
     62	MT6358_IRQ_VLDO28_OC,
     63	MT6358_IRQ_VA12_OC,
     64	MT6358_IRQ_VAUX18_OC,
     65	MT6358_IRQ_VAUD28_OC,
     66	MT6358_IRQ_VIO28_OC,
     67	MT6358_IRQ_VIO18_OC,
     68	MT6358_IRQ_VSRAM_PROC11_OC,
     69	MT6358_IRQ_VSRAM_PROC12_OC,
     70	MT6358_IRQ_VSRAM_OTHERS_OC,
     71	MT6358_IRQ_VSRAM_GPU_OC,
     72	MT6358_IRQ_VDRAM2_OC,
     73	MT6358_IRQ_VMC_OC,
     74	MT6358_IRQ_VMCH_OC,
     75	MT6358_IRQ_VEMC_OC,
     76	MT6358_IRQ_VSIM1_OC,
     77	MT6358_IRQ_VSIM2_OC,
     78	MT6358_IRQ_VIBR_OC,
     79	MT6358_IRQ_VUSB_OC,
     80	MT6358_IRQ_VBIF28_OC,
     81	MT6358_IRQ_PWRKEY = 48,
     82	MT6358_IRQ_HOMEKEY,
     83	MT6358_IRQ_PWRKEY_R,
     84	MT6358_IRQ_HOMEKEY_R,
     85	MT6358_IRQ_NI_LBAT_INT,
     86	MT6358_IRQ_CHRDET,
     87	MT6358_IRQ_CHRDET_EDGE,
     88	MT6358_IRQ_VCDT_HV_DET,
     89	MT6358_IRQ_RTC = 64,
     90	MT6358_IRQ_FG_BAT0_H = 80,
     91	MT6358_IRQ_FG_BAT0_L,
     92	MT6358_IRQ_FG_CUR_H,
     93	MT6358_IRQ_FG_CUR_L,
     94	MT6358_IRQ_FG_ZCV,
     95	MT6358_IRQ_FG_BAT1_H,
     96	MT6358_IRQ_FG_BAT1_L,
     97	MT6358_IRQ_FG_N_CHARGE_L,
     98	MT6358_IRQ_FG_IAVG_H,
     99	MT6358_IRQ_FG_IAVG_L,
    100	MT6358_IRQ_FG_TIME_H,
    101	MT6358_IRQ_FG_DISCHARGE,
    102	MT6358_IRQ_FG_CHARGE,
    103	MT6358_IRQ_BATON_LV = 96,
    104	MT6358_IRQ_BATON_HT,
    105	MT6358_IRQ_BATON_BAT_IN,
    106	MT6358_IRQ_BATON_BAT_OUT,
    107	MT6358_IRQ_BIF,
    108	MT6358_IRQ_BAT_H = 112,
    109	MT6358_IRQ_BAT_L,
    110	MT6358_IRQ_BAT2_H,
    111	MT6358_IRQ_BAT2_L,
    112	MT6358_IRQ_BAT_TEMP_H,
    113	MT6358_IRQ_BAT_TEMP_L,
    114	MT6358_IRQ_AUXADC_IMP,
    115	MT6358_IRQ_NAG_C_DLTV,
    116	MT6358_IRQ_AUDIO = 128,
    117	MT6358_IRQ_ACCDET = 133,
    118	MT6358_IRQ_ACCDET_EINT0,
    119	MT6358_IRQ_ACCDET_EINT1,
    120	MT6358_IRQ_SPI_CMD_ALERT = 144,
    121	MT6358_IRQ_NR,
    122};
    123
    124#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
    125#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
    126#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
    127#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
    128#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
    129#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
    130#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
    131#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
    132
    133#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
    134#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
    135#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
    136#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
    137#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
    138#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
    139#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
    140#define MT6358_IRQ_MISC_BITS	\
    141	(MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
    142
    143#define MT6358_TOP_GEN(sp)	\
    144{	\
    145	.hwirq_base = MT6358_IRQ_##sp##_BASE,	\
    146	.num_int_regs =	\
    147		((MT6358_IRQ_##sp##_BITS - 1) /	\
    148		MTK_PMIC_REG_WIDTH) + 1,	\
    149	.en_reg = MT6358_##sp##_TOP_INT_CON0,	\
    150	.en_reg_shift = 0x6,	\
    151	.sta_reg = MT6358_##sp##_TOP_INT_STATUS0,	\
    152	.sta_reg_shift = 0x2,	\
    153	.top_offset = MT6358_##sp##_TOP,	\
    154}
    155
    156#endif /* __MFD_MT6358_CORE_H__ */