cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pmic.h (1957B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __LINUX_MFD_PCF50633_PMIC_H
      3#define __LINUX_MFD_PCF50633_PMIC_H
      4
      5#include <linux/mfd/pcf50633/core.h>
      6#include <linux/platform_device.h>
      7
      8#define PCF50633_REG_AUTOOUT	0x1a
      9#define PCF50633_REG_AUTOENA	0x1b
     10#define PCF50633_REG_AUTOCTL	0x1c
     11#define PCF50633_REG_AUTOMXC	0x1d
     12#define PCF50633_REG_DOWN1OUT	0x1e
     13#define PCF50633_REG_DOWN1ENA	0x1f
     14#define PCF50633_REG_DOWN1CTL	0x20
     15#define PCF50633_REG_DOWN1MXC	0x21
     16#define PCF50633_REG_DOWN2OUT	0x22
     17#define PCF50633_REG_DOWN2ENA	0x23
     18#define PCF50633_REG_DOWN2CTL	0x24
     19#define PCF50633_REG_DOWN2MXC	0x25
     20#define PCF50633_REG_MEMLDOOUT	0x26
     21#define PCF50633_REG_MEMLDOENA	0x27
     22#define PCF50633_REG_LDO1OUT	0x2d
     23#define PCF50633_REG_LDO1ENA	0x2e
     24#define PCF50633_REG_LDO2OUT	0x2f
     25#define PCF50633_REG_LDO2ENA	0x30
     26#define PCF50633_REG_LDO3OUT	0x31
     27#define PCF50633_REG_LDO3ENA	0x32
     28#define PCF50633_REG_LDO4OUT	0x33
     29#define PCF50633_REG_LDO4ENA	0x34
     30#define PCF50633_REG_LDO5OUT	0x35
     31#define PCF50633_REG_LDO5ENA	0x36
     32#define PCF50633_REG_LDO6OUT	0x37
     33#define PCF50633_REG_LDO6ENA	0x38
     34#define PCF50633_REG_HCLDOOUT	0x39
     35#define PCF50633_REG_HCLDOENA	0x3a
     36#define PCF50633_REG_HCLDOOVL	0x40
     37
     38enum pcf50633_regulator_enable {
     39	PCF50633_REGULATOR_ON		= 0x01,
     40	PCF50633_REGULATOR_ON_GPIO1	= 0x02,
     41	PCF50633_REGULATOR_ON_GPIO2	= 0x04,
     42	PCF50633_REGULATOR_ON_GPIO3	= 0x08,
     43};
     44#define PCF50633_REGULATOR_ON_MASK	0x0f
     45
     46enum pcf50633_regulator_phase {
     47	PCF50633_REGULATOR_ACTPH1	= 0x00,
     48	PCF50633_REGULATOR_ACTPH2	= 0x10,
     49	PCF50633_REGULATOR_ACTPH3	= 0x20,
     50	PCF50633_REGULATOR_ACTPH4	= 0x30,
     51};
     52#define PCF50633_REGULATOR_ACTPH_MASK	0x30
     53
     54enum pcf50633_regulator_id {
     55	PCF50633_REGULATOR_AUTO,
     56	PCF50633_REGULATOR_DOWN1,
     57	PCF50633_REGULATOR_DOWN2,
     58	PCF50633_REGULATOR_LDO1,
     59	PCF50633_REGULATOR_LDO2,
     60	PCF50633_REGULATOR_LDO3,
     61	PCF50633_REGULATOR_LDO4,
     62	PCF50633_REGULATOR_LDO5,
     63	PCF50633_REGULATOR_LDO6,
     64	PCF50633_REGULATOR_HCLDO,
     65	PCF50633_REGULATOR_MEMLDO,
     66};
     67#endif
     68