cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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rohm-bd718x7.h (9038B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/* Copyright (C) 2018 ROHM Semiconductors */
      3
      4#ifndef __LINUX_MFD_BD718XX_H__
      5#define __LINUX_MFD_BD718XX_H__
      6
      7#include <linux/mfd/rohm-generic.h>
      8#include <linux/regmap.h>
      9
     10enum {
     11	BD718XX_BUCK1 = 0,
     12	BD718XX_BUCK2,
     13	BD718XX_BUCK3,
     14	BD718XX_BUCK4,
     15	BD718XX_BUCK5,
     16	BD718XX_BUCK6,
     17	BD718XX_BUCK7,
     18	BD718XX_BUCK8,
     19	BD718XX_LDO1,
     20	BD718XX_LDO2,
     21	BD718XX_LDO3,
     22	BD718XX_LDO4,
     23	BD718XX_LDO5,
     24	BD718XX_LDO6,
     25	BD718XX_LDO7,
     26	BD718XX_REGULATOR_AMOUNT,
     27};
     28
     29/* Common voltage configurations */
     30#define BD718XX_DVS_BUCK_VOLTAGE_NUM		0x3D
     31#define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM	0x3D
     32
     33#define BD718XX_LDO1_VOLTAGE_NUM	0x08
     34#define BD718XX_LDO2_VOLTAGE_NUM	0x02
     35#define BD718XX_LDO3_VOLTAGE_NUM	0x10
     36#define BD718XX_LDO4_VOLTAGE_NUM	0x0A
     37#define BD718XX_LDO6_VOLTAGE_NUM	0x0A
     38
     39/* BD71837 specific voltage configurations */
     40#define BD71837_BUCK5_VOLTAGE_NUM	0x10
     41#define BD71837_BUCK6_VOLTAGE_NUM	0x04
     42#define BD71837_BUCK7_VOLTAGE_NUM	0x08
     43#define BD71837_LDO5_VOLTAGE_NUM	0x10
     44#define BD71837_LDO7_VOLTAGE_NUM	0x10
     45
     46/* BD71847 specific voltage configurations */
     47#define BD71847_BUCK3_VOLTAGE_NUM	0x18
     48#define BD71847_BUCK4_VOLTAGE_NUM	0x08
     49#define BD71847_LDO5_VOLTAGE_NUM	0x20
     50
     51/* Registers specific to BD71837 */
     52enum {
     53	BD71837_REG_BUCK3_CTRL =	0x07,
     54	BD71837_REG_BUCK4_CTRL =	0x08,
     55	BD71837_REG_BUCK3_VOLT_RUN =	0x12,
     56	BD71837_REG_BUCK4_VOLT_RUN =	0x13,
     57	BD71837_REG_LDO7_VOLT =		0x1E,
     58};
     59
     60/* Registers common for BD71837 and BD71847 */
     61enum {
     62	BD718XX_REG_REV =			0x00,
     63	BD718XX_REG_SWRESET =			0x01,
     64	BD718XX_REG_I2C_DEV =			0x02,
     65	BD718XX_REG_PWRCTRL0 =			0x03,
     66	BD718XX_REG_PWRCTRL1 =			0x04,
     67	BD718XX_REG_BUCK1_CTRL =		0x05,
     68	BD718XX_REG_BUCK2_CTRL =		0x06,
     69	BD718XX_REG_1ST_NODVS_BUCK_CTRL =	0x09,
     70	BD718XX_REG_2ND_NODVS_BUCK_CTRL =	0x0A,
     71	BD718XX_REG_3RD_NODVS_BUCK_CTRL =	0x0B,
     72	BD718XX_REG_4TH_NODVS_BUCK_CTRL =	0x0C,
     73	BD718XX_REG_BUCK1_VOLT_RUN =		0x0D,
     74	BD718XX_REG_BUCK1_VOLT_IDLE =		0x0E,
     75	BD718XX_REG_BUCK1_VOLT_SUSP =		0x0F,
     76	BD718XX_REG_BUCK2_VOLT_RUN =		0x10,
     77	BD718XX_REG_BUCK2_VOLT_IDLE =		0x11,
     78	BD718XX_REG_1ST_NODVS_BUCK_VOLT =	0x14,
     79	BD718XX_REG_2ND_NODVS_BUCK_VOLT =	0x15,
     80	BD718XX_REG_3RD_NODVS_BUCK_VOLT =	0x16,
     81	BD718XX_REG_4TH_NODVS_BUCK_VOLT =	0x17,
     82	BD718XX_REG_LDO1_VOLT =			0x18,
     83	BD718XX_REG_LDO2_VOLT =			0x19,
     84	BD718XX_REG_LDO3_VOLT =			0x1A,
     85	BD718XX_REG_LDO4_VOLT =			0x1B,
     86	BD718XX_REG_LDO5_VOLT =			0x1C,
     87	BD718XX_REG_LDO6_VOLT =			0x1D,
     88	BD718XX_REG_TRANS_COND0 =		0x1F,
     89	BD718XX_REG_TRANS_COND1 =		0x20,
     90	BD718XX_REG_VRFAULTEN =			0x21,
     91	BD718XX_REG_MVRFLTMASK0 =		0x22,
     92	BD718XX_REG_MVRFLTMASK1 =		0x23,
     93	BD718XX_REG_MVRFLTMASK2 =		0x24,
     94	BD718XX_REG_RCVCFG =			0x25,
     95	BD718XX_REG_RCVNUM =			0x26,
     96	BD718XX_REG_PWRONCONFIG0 =		0x27,
     97	BD718XX_REG_PWRONCONFIG1 =		0x28,
     98	BD718XX_REG_RESETSRC =			0x29,
     99	BD718XX_REG_MIRQ =			0x2A,
    100	BD718XX_REG_IRQ =			0x2B,
    101	BD718XX_REG_IN_MON =			0x2C,
    102	BD718XX_REG_POW_STATE =			0x2D,
    103	BD718XX_REG_OUT32K =			0x2E,
    104	BD718XX_REG_REGLOCK =			0x2F,
    105	BD718XX_REG_OTPVER =			0xFF,
    106	BD718XX_MAX_REGISTER =			0x100,
    107};
    108
    109#define REGLOCK_PWRSEQ	0x1
    110#define REGLOCK_VREG	0x10
    111
    112/* Generic BUCK control masks */
    113#define BD718XX_BUCK_SEL	0x02
    114#define BD718XX_BUCK_EN		0x01
    115#define BD718XX_BUCK_RUN_ON	0x04
    116
    117/* Generic LDO masks */
    118#define BD718XX_LDO_SEL		0x80
    119#define BD718XX_LDO_EN		0x40
    120
    121/* BD71837 BUCK ramp rate CTRL reg bits */
    122#define BUCK_RAMPRATE_MASK	0xC0
    123#define BUCK_RAMPRATE_10P00MV	0x0
    124#define BUCK_RAMPRATE_5P00MV	0x1
    125#define BUCK_RAMPRATE_2P50MV	0x2
    126#define BUCK_RAMPRATE_1P25MV	0x3
    127
    128#define DVS_BUCK_RUN_MASK	0x3F
    129#define DVS_BUCK_SUSP_MASK	0x3F
    130#define DVS_BUCK_IDLE_MASK	0x3F
    131
    132#define BD718XX_1ST_NODVS_BUCK_MASK	0x07
    133#define BD718XX_3RD_NODVS_BUCK_MASK	0x07
    134#define BD718XX_4TH_NODVS_BUCK_MASK	0x3F
    135
    136#define BD71847_BUCK3_MASK		0x07
    137#define BD71847_BUCK3_RANGE_MASK	0xC0
    138#define BD71847_BUCK4_MASK		0x03
    139#define BD71847_BUCK4_RANGE_MASK	0x40
    140
    141#define BD71837_BUCK5_MASK		0x07
    142#define BD71837_BUCK5_RANGE_MASK	0x80
    143#define BD71837_BUCK6_MASK		0x03
    144
    145#define BD718XX_LDO1_MASK		0x03
    146#define BD718XX_LDO1_RANGE_MASK		0x20
    147#define BD718XX_LDO2_MASK		0x20
    148#define BD718XX_LDO3_MASK		0x0F
    149#define BD718XX_LDO4_MASK		0x0F
    150#define BD718XX_LDO6_MASK		0x0F
    151
    152#define BD71837_LDO5_MASK		0x0F
    153#define BD71847_LDO5_MASK		0x0F
    154#define BD71847_LDO5_RANGE_MASK		0x20
    155
    156#define BD71837_LDO7_MASK		0x0F
    157
    158/* BD718XX Voltage monitoring masks */
    159#define BD718XX_BUCK1_VRMON80           0x1
    160#define BD718XX_BUCK1_VRMON130          0x2
    161#define BD718XX_BUCK2_VRMON80           0x4
    162#define BD718XX_BUCK2_VRMON130          0x8
    163#define BD718XX_1ST_NODVS_BUCK_VRMON80  0x1
    164#define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2
    165#define BD718XX_2ND_NODVS_BUCK_VRMON80  0x4
    166#define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8
    167#define BD718XX_3RD_NODVS_BUCK_VRMON80  0x10
    168#define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20
    169#define BD718XX_4TH_NODVS_BUCK_VRMON80  0x40
    170#define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80
    171#define BD718XX_LDO1_VRMON80            0x1
    172#define BD718XX_LDO2_VRMON80            0x2
    173#define BD718XX_LDO3_VRMON80            0x4
    174#define BD718XX_LDO4_VRMON80            0x8
    175#define BD718XX_LDO5_VRMON80            0x10
    176#define BD718XX_LDO6_VRMON80            0x20
    177
    178/* BD71837 specific voltage monitoring masks */
    179#define BD71837_BUCK3_VRMON80           0x10
    180#define BD71837_BUCK3_VRMON130          0x20
    181#define BD71837_BUCK4_VRMON80           0x40
    182#define BD71837_BUCK4_VRMON130          0x80
    183#define BD71837_LDO7_VRMON80            0x40
    184
    185/* BD718XX_REG_IRQ bits */
    186#define IRQ_SWRST		0x40
    187#define IRQ_PWRON_S		0x20
    188#define IRQ_PWRON_L		0x10
    189#define IRQ_PWRON		0x08
    190#define IRQ_WDOG		0x04
    191#define IRQ_ON_REQ		0x02
    192#define IRQ_STBY_REQ		0x01
    193
    194/* ROHM BD718XX irqs */
    195enum {
    196	BD718XX_INT_STBY_REQ,
    197	BD718XX_INT_ON_REQ,
    198	BD718XX_INT_WDOG,
    199	BD718XX_INT_PWRBTN,
    200	BD718XX_INT_PWRBTN_L,
    201	BD718XX_INT_PWRBTN_S,
    202	BD718XX_INT_SWRST
    203};
    204
    205/* ROHM BD718XX interrupt masks */
    206#define BD718XX_INT_SWRST_MASK		0x40
    207#define BD718XX_INT_PWRBTN_S_MASK	0x20
    208#define BD718XX_INT_PWRBTN_L_MASK	0x10
    209#define BD718XX_INT_PWRBTN_MASK		0x8
    210#define BD718XX_INT_WDOG_MASK		0x4
    211#define BD718XX_INT_ON_REQ_MASK		0x2
    212#define BD718XX_INT_STBY_REQ_MASK	0x1
    213
    214/* Register write induced reset settings */
    215
    216/*
    217 * Even though the bit zero is not SWRESET type we still want to write zero
    218 * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we
    219 * write 1 to it we will trigger the action. So always write 0 to it when
    220 * changning SWRESET action - no matter what we read from it.
    221 */
    222#define BD718XX_SWRESET_TYPE_MASK	7
    223#define BD718XX_SWRESET_TYPE_DISABLED	0
    224#define BD718XX_SWRESET_TYPE_COLD	4
    225#define BD718XX_SWRESET_TYPE_WARM	6
    226
    227#define BD718XX_SWRESET_RESET_MASK	1
    228#define BD718XX_SWRESET_RESET		1
    229
    230/* Poweroff state transition conditions */
    231
    232#define BD718XX_ON_REQ_POWEROFF_MASK	1
    233#define BD718XX_SWRESET_POWEROFF_MASK	2
    234#define BD718XX_WDOG_POWEROFF_MASK	4
    235#define BD718XX_KEY_L_POWEROFF_MASK	8
    236
    237#define BD718XX_POWOFF_TO_SNVS	0
    238#define BD718XX_POWOFF_TO_RDY	0xF
    239
    240#define BD718XX_POWOFF_TIME_MASK 0xF0
    241enum {
    242	BD718XX_POWOFF_TIME_5MS = 0,
    243	BD718XX_POWOFF_TIME_10MS,
    244	BD718XX_POWOFF_TIME_15MS,
    245	BD718XX_POWOFF_TIME_20MS,
    246	BD718XX_POWOFF_TIME_25MS,
    247	BD718XX_POWOFF_TIME_30MS,
    248	BD718XX_POWOFF_TIME_35MS,
    249	BD718XX_POWOFF_TIME_40MS,
    250	BD718XX_POWOFF_TIME_45MS,
    251	BD718XX_POWOFF_TIME_50MS,
    252	BD718XX_POWOFF_TIME_75MS,
    253	BD718XX_POWOFF_TIME_100MS,
    254	BD718XX_POWOFF_TIME_250MS,
    255	BD718XX_POWOFF_TIME_500MS,
    256	BD718XX_POWOFF_TIME_750MS,
    257	BD718XX_POWOFF_TIME_1500MS
    258};
    259
    260/* Poweron sequence state transition conditions */
    261#define BD718XX_RDY_TO_SNVS_MASK 0xF
    262#define BD718XX_SNVS_TO_RUN_MASK 0xF0
    263
    264#define BD718XX_PWR_TRIG_KEY_L		1
    265#define BD718XX_PWR_TRIG_KEY_S		2
    266#define BD718XX_PWR_TRIG_PMIC_ON	4
    267#define BD718XX_PWR_TRIG_VSYS_UVLO	8
    268#define BD718XX_RDY_TO_SNVS_SIFT	0
    269#define BD718XX_SNVS_TO_RUN_SIFT	4
    270
    271#define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF
    272
    273/* Timeout value for detecting short press */
    274enum {
    275	BD718XX_PWRBTN_SHORT_PRESS_10MS = 0,
    276	BD718XX_PWRBTN_SHORT_PRESS_500MS,
    277	BD718XX_PWRBTN_SHORT_PRESS_1000MS,
    278	BD718XX_PWRBTN_SHORT_PRESS_1500MS,
    279	BD718XX_PWRBTN_SHORT_PRESS_2000MS,
    280	BD718XX_PWRBTN_SHORT_PRESS_2500MS,
    281	BD718XX_PWRBTN_SHORT_PRESS_3000MS,
    282	BD718XX_PWRBTN_SHORT_PRESS_3500MS,
    283	BD718XX_PWRBTN_SHORT_PRESS_4000MS,
    284	BD718XX_PWRBTN_SHORT_PRESS_4500MS,
    285	BD718XX_PWRBTN_SHORT_PRESS_5000MS,
    286	BD718XX_PWRBTN_SHORT_PRESS_5500MS,
    287	BD718XX_PWRBTN_SHORT_PRESS_6000MS,
    288	BD718XX_PWRBTN_SHORT_PRESS_6500MS,
    289	BD718XX_PWRBTN_SHORT_PRESS_7000MS,
    290	BD718XX_PWRBTN_SHORT_PRESS_7500MS
    291};
    292
    293/* Timeout value for detecting LONG press */
    294enum {
    295	BD718XX_PWRBTN_LONG_PRESS_10MS = 0,
    296	BD718XX_PWRBTN_LONG_PRESS_1S,
    297	BD718XX_PWRBTN_LONG_PRESS_2S,
    298	BD718XX_PWRBTN_LONG_PRESS_3S,
    299	BD718XX_PWRBTN_LONG_PRESS_4S,
    300	BD718XX_PWRBTN_LONG_PRESS_5S,
    301	BD718XX_PWRBTN_LONG_PRESS_6S,
    302	BD718XX_PWRBTN_LONG_PRESS_7S,
    303	BD718XX_PWRBTN_LONG_PRESS_8S,
    304	BD718XX_PWRBTN_LONG_PRESS_9S,
    305	BD718XX_PWRBTN_LONG_PRESS_10S,
    306	BD718XX_PWRBTN_LONG_PRESS_11S,
    307	BD718XX_PWRBTN_LONG_PRESS_12S,
    308	BD718XX_PWRBTN_LONG_PRESS_13S,
    309	BD718XX_PWRBTN_LONG_PRESS_14S,
    310	BD718XX_PWRBTN_LONG_PRESS_15S
    311};
    312
    313#endif /* __LINUX_MFD_BD718XX_H__ */