cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.h (5763B)

      1/* SPDX-License-Identifier: GPL-2.0+ */
      2/*
      3 * Copyright (c) 2012 Samsung Electronics Co., Ltd
      4 *              http://www.samsung.com
      5 */
      6
      7#ifndef __LINUX_MFD_SEC_IRQ_H
      8#define __LINUX_MFD_SEC_IRQ_H
      9
     10enum s2mpa01_irq {
     11	S2MPA01_IRQ_PWRONF,
     12	S2MPA01_IRQ_PWRONR,
     13	S2MPA01_IRQ_JIGONBF,
     14	S2MPA01_IRQ_JIGONBR,
     15	S2MPA01_IRQ_ACOKBF,
     16	S2MPA01_IRQ_ACOKBR,
     17	S2MPA01_IRQ_PWRON1S,
     18	S2MPA01_IRQ_MRB,
     19
     20	S2MPA01_IRQ_RTC60S,
     21	S2MPA01_IRQ_RTCA1,
     22	S2MPA01_IRQ_RTCA0,
     23	S2MPA01_IRQ_SMPL,
     24	S2MPA01_IRQ_RTC1S,
     25	S2MPA01_IRQ_WTSR,
     26
     27	S2MPA01_IRQ_INT120C,
     28	S2MPA01_IRQ_INT140C,
     29	S2MPA01_IRQ_LDO3_TSD,
     30	S2MPA01_IRQ_B16_TSD,
     31	S2MPA01_IRQ_B24_TSD,
     32	S2MPA01_IRQ_B35_TSD,
     33
     34	S2MPA01_IRQ_NR,
     35};
     36
     37#define S2MPA01_IRQ_PWRONF_MASK		(1 << 0)
     38#define S2MPA01_IRQ_PWRONR_MASK		(1 << 1)
     39#define S2MPA01_IRQ_JIGONBF_MASK	(1 << 2)
     40#define S2MPA01_IRQ_JIGONBR_MASK	(1 << 3)
     41#define S2MPA01_IRQ_ACOKBF_MASK		(1 << 4)
     42#define S2MPA01_IRQ_ACOKBR_MASK		(1 << 5)
     43#define S2MPA01_IRQ_PWRON1S_MASK	(1 << 6)
     44#define S2MPA01_IRQ_MRB_MASK		(1 << 7)
     45
     46#define S2MPA01_IRQ_RTC60S_MASK		(1 << 0)
     47#define S2MPA01_IRQ_RTCA1_MASK		(1 << 1)
     48#define S2MPA01_IRQ_RTCA0_MASK		(1 << 2)
     49#define S2MPA01_IRQ_SMPL_MASK		(1 << 3)
     50#define S2MPA01_IRQ_RTC1S_MASK		(1 << 4)
     51#define S2MPA01_IRQ_WTSR_MASK		(1 << 5)
     52
     53#define S2MPA01_IRQ_INT120C_MASK	(1 << 0)
     54#define S2MPA01_IRQ_INT140C_MASK	(1 << 1)
     55#define S2MPA01_IRQ_LDO3_TSD_MASK	(1 << 2)
     56#define S2MPA01_IRQ_B16_TSD_MASK	(1 << 3)
     57#define S2MPA01_IRQ_B24_TSD_MASK	(1 << 4)
     58#define S2MPA01_IRQ_B35_TSD_MASK	(1 << 5)
     59
     60enum s2mps11_irq {
     61	S2MPS11_IRQ_PWRONF,
     62	S2MPS11_IRQ_PWRONR,
     63	S2MPS11_IRQ_JIGONBF,
     64	S2MPS11_IRQ_JIGONBR,
     65	S2MPS11_IRQ_ACOKBF,
     66	S2MPS11_IRQ_ACOKBR,
     67	S2MPS11_IRQ_PWRON1S,
     68	S2MPS11_IRQ_MRB,
     69
     70	S2MPS11_IRQ_RTC60S,
     71	S2MPS11_IRQ_RTCA1,
     72	S2MPS11_IRQ_RTCA0,
     73	S2MPS11_IRQ_SMPL,
     74	S2MPS11_IRQ_RTC1S,
     75	S2MPS11_IRQ_WTSR,
     76
     77	S2MPS11_IRQ_INT120C,
     78	S2MPS11_IRQ_INT140C,
     79
     80	S2MPS11_IRQ_NR,
     81};
     82
     83#define S2MPS11_IRQ_PWRONF_MASK		(1 << 0)
     84#define S2MPS11_IRQ_PWRONR_MASK		(1 << 1)
     85#define S2MPS11_IRQ_JIGONBF_MASK	(1 << 2)
     86#define S2MPS11_IRQ_JIGONBR_MASK	(1 << 3)
     87#define S2MPS11_IRQ_ACOKBF_MASK		(1 << 4)
     88#define S2MPS11_IRQ_ACOKBR_MASK		(1 << 5)
     89#define S2MPS11_IRQ_PWRON1S_MASK	(1 << 6)
     90#define S2MPS11_IRQ_MRB_MASK		(1 << 7)
     91
     92#define S2MPS11_IRQ_RTC60S_MASK		(1 << 0)
     93#define S2MPS11_IRQ_RTCA1_MASK		(1 << 1)
     94#define S2MPS11_IRQ_RTCA0_MASK		(1 << 2)
     95#define S2MPS11_IRQ_SMPL_MASK		(1 << 3)
     96#define S2MPS11_IRQ_RTC1S_MASK		(1 << 4)
     97#define S2MPS11_IRQ_WTSR_MASK		(1 << 5)
     98
     99#define S2MPS11_IRQ_INT120C_MASK	(1 << 0)
    100#define S2MPS11_IRQ_INT140C_MASK	(1 << 1)
    101
    102enum s2mps14_irq {
    103	S2MPS14_IRQ_PWRONF,
    104	S2MPS14_IRQ_PWRONR,
    105	S2MPS14_IRQ_JIGONBF,
    106	S2MPS14_IRQ_JIGONBR,
    107	S2MPS14_IRQ_ACOKBF,
    108	S2MPS14_IRQ_ACOKBR,
    109	S2MPS14_IRQ_PWRON1S,
    110	S2MPS14_IRQ_MRB,
    111
    112	S2MPS14_IRQ_RTC60S,
    113	S2MPS14_IRQ_RTCA1,
    114	S2MPS14_IRQ_RTCA0,
    115	S2MPS14_IRQ_SMPL,
    116	S2MPS14_IRQ_RTC1S,
    117	S2MPS14_IRQ_WTSR,
    118
    119	S2MPS14_IRQ_INT120C,
    120	S2MPS14_IRQ_INT140C,
    121	S2MPS14_IRQ_TSD,
    122
    123	S2MPS14_IRQ_NR,
    124};
    125
    126enum s2mpu02_irq {
    127	S2MPU02_IRQ_PWRONF,
    128	S2MPU02_IRQ_PWRONR,
    129	S2MPU02_IRQ_JIGONBF,
    130	S2MPU02_IRQ_JIGONBR,
    131	S2MPU02_IRQ_ACOKBF,
    132	S2MPU02_IRQ_ACOKBR,
    133	S2MPU02_IRQ_PWRON1S,
    134	S2MPU02_IRQ_MRB,
    135
    136	S2MPU02_IRQ_RTC60S,
    137	S2MPU02_IRQ_RTCA1,
    138	S2MPU02_IRQ_RTCA0,
    139	S2MPU02_IRQ_SMPL,
    140	S2MPU02_IRQ_RTC1S,
    141	S2MPU02_IRQ_WTSR,
    142
    143	S2MPU02_IRQ_INT120C,
    144	S2MPU02_IRQ_INT140C,
    145	S2MPU02_IRQ_TSD,
    146
    147	S2MPU02_IRQ_NR,
    148};
    149
    150/* Masks for interrupts are the same as in s2mps11 */
    151#define S2MPS14_IRQ_TSD_MASK		(1 << 2)
    152
    153enum s5m8767_irq {
    154	S5M8767_IRQ_PWRR,
    155	S5M8767_IRQ_PWRF,
    156	S5M8767_IRQ_PWR1S,
    157	S5M8767_IRQ_JIGR,
    158	S5M8767_IRQ_JIGF,
    159	S5M8767_IRQ_LOWBAT2,
    160	S5M8767_IRQ_LOWBAT1,
    161
    162	S5M8767_IRQ_MRB,
    163	S5M8767_IRQ_DVSOK2,
    164	S5M8767_IRQ_DVSOK3,
    165	S5M8767_IRQ_DVSOK4,
    166
    167	S5M8767_IRQ_RTC60S,
    168	S5M8767_IRQ_RTCA1,
    169	S5M8767_IRQ_RTCA2,
    170	S5M8767_IRQ_SMPL,
    171	S5M8767_IRQ_RTC1S,
    172	S5M8767_IRQ_WTSR,
    173
    174	S5M8767_IRQ_NR,
    175};
    176
    177#define S5M8767_IRQ_PWRR_MASK		(1 << 0)
    178#define S5M8767_IRQ_PWRF_MASK		(1 << 1)
    179#define S5M8767_IRQ_PWR1S_MASK		(1 << 3)
    180#define S5M8767_IRQ_JIGR_MASK		(1 << 4)
    181#define S5M8767_IRQ_JIGF_MASK		(1 << 5)
    182#define S5M8767_IRQ_LOWBAT2_MASK	(1 << 6)
    183#define S5M8767_IRQ_LOWBAT1_MASK	(1 << 7)
    184
    185#define S5M8767_IRQ_MRB_MASK		(1 << 2)
    186#define S5M8767_IRQ_DVSOK2_MASK		(1 << 3)
    187#define S5M8767_IRQ_DVSOK3_MASK		(1 << 4)
    188#define S5M8767_IRQ_DVSOK4_MASK		(1 << 5)
    189
    190#define S5M8767_IRQ_RTC60S_MASK		(1 << 0)
    191#define S5M8767_IRQ_RTCA1_MASK		(1 << 1)
    192#define S5M8767_IRQ_RTCA2_MASK		(1 << 2)
    193#define S5M8767_IRQ_SMPL_MASK		(1 << 3)
    194#define S5M8767_IRQ_RTC1S_MASK		(1 << 4)
    195#define S5M8767_IRQ_WTSR_MASK		(1 << 5)
    196
    197enum s5m8763_irq {
    198	S5M8763_IRQ_DCINF,
    199	S5M8763_IRQ_DCINR,
    200	S5M8763_IRQ_JIGF,
    201	S5M8763_IRQ_JIGR,
    202	S5M8763_IRQ_PWRONF,
    203	S5M8763_IRQ_PWRONR,
    204
    205	S5M8763_IRQ_WTSREVNT,
    206	S5M8763_IRQ_SMPLEVNT,
    207	S5M8763_IRQ_ALARM1,
    208	S5M8763_IRQ_ALARM0,
    209
    210	S5M8763_IRQ_ONKEY1S,
    211	S5M8763_IRQ_TOPOFFR,
    212	S5M8763_IRQ_DCINOVPR,
    213	S5M8763_IRQ_CHGRSTF,
    214	S5M8763_IRQ_DONER,
    215	S5M8763_IRQ_CHGFAULT,
    216
    217	S5M8763_IRQ_LOBAT1,
    218	S5M8763_IRQ_LOBAT2,
    219
    220	S5M8763_IRQ_NR,
    221};
    222
    223#define S5M8763_IRQ_DCINF_MASK		(1 << 2)
    224#define S5M8763_IRQ_DCINR_MASK		(1 << 3)
    225#define S5M8763_IRQ_JIGF_MASK		(1 << 4)
    226#define S5M8763_IRQ_JIGR_MASK		(1 << 5)
    227#define S5M8763_IRQ_PWRONF_MASK		(1 << 6)
    228#define S5M8763_IRQ_PWRONR_MASK		(1 << 7)
    229
    230#define S5M8763_IRQ_WTSREVNT_MASK	(1 << 0)
    231#define S5M8763_IRQ_SMPLEVNT_MASK	(1 << 1)
    232#define S5M8763_IRQ_ALARM1_MASK		(1 << 2)
    233#define S5M8763_IRQ_ALARM0_MASK		(1 << 3)
    234
    235#define S5M8763_IRQ_ONKEY1S_MASK	(1 << 0)
    236#define S5M8763_IRQ_TOPOFFR_MASK	(1 << 2)
    237#define S5M8763_IRQ_DCINOVPR_MASK	(1 << 3)
    238#define S5M8763_IRQ_CHGRSTF_MASK	(1 << 4)
    239#define S5M8763_IRQ_DONER_MASK		(1 << 5)
    240#define S5M8763_IRQ_CHGFAULT_MASK	(1 << 7)
    241
    242#define S5M8763_IRQ_LOBAT1_MASK		(1 << 0)
    243#define S5M8763_IRQ_LOBAT2_MASK		(1 << 1)
    244
    245#define S5M8763_ENRAMP                  (1 << 4)
    246
    247#endif /*  __LINUX_MFD_SEC_IRQ_H */