cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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atmel-smc.h (4613B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Atmel SMC (Static Memory Controller) register offsets and bit definitions.
      4 *
      5 * Copyright (C) 2014 Atmel
      6 * Copyright (C) 2014 Free Electrons
      7 *
      8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
      9 */
     10
     11#ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
     12#define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
     13
     14#include <linux/kernel.h>
     15#include <linux/of.h>
     16#include <linux/regmap.h>
     17
     18#define ATMEL_SMC_SETUP(cs)			(((cs) * 0x10))
     19#define ATMEL_HSMC_SETUP(layout, cs)		\
     20	((layout)->timing_regs_offset + ((cs) * 0x14))
     21#define ATMEL_SMC_PULSE(cs)			(((cs) * 0x10) + 0x4)
     22#define ATMEL_HSMC_PULSE(layout, cs)		\
     23	((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
     24#define ATMEL_SMC_CYCLE(cs)			(((cs) * 0x10) + 0x8)
     25#define ATMEL_HSMC_CYCLE(layout, cs)			\
     26	((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
     27#define ATMEL_SMC_NWE_SHIFT			0
     28#define ATMEL_SMC_NCS_WR_SHIFT			8
     29#define ATMEL_SMC_NRD_SHIFT			16
     30#define ATMEL_SMC_NCS_RD_SHIFT			24
     31
     32#define ATMEL_SMC_MODE(cs)			(((cs) * 0x10) + 0xc)
     33#define ATMEL_HSMC_MODE(layout, cs)			\
     34	((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
     35#define ATMEL_SMC_MODE_READMODE_MASK		BIT(0)
     36#define ATMEL_SMC_MODE_READMODE_NCS		(0 << 0)
     37#define ATMEL_SMC_MODE_READMODE_NRD		(1 << 0)
     38#define ATMEL_SMC_MODE_WRITEMODE_MASK		BIT(1)
     39#define ATMEL_SMC_MODE_WRITEMODE_NCS		(0 << 1)
     40#define ATMEL_SMC_MODE_WRITEMODE_NWE		(1 << 1)
     41#define ATMEL_SMC_MODE_EXNWMODE_MASK		GENMASK(5, 4)
     42#define ATMEL_SMC_MODE_EXNWMODE_DISABLE		(0 << 4)
     43#define ATMEL_SMC_MODE_EXNWMODE_FROZEN		(2 << 4)
     44#define ATMEL_SMC_MODE_EXNWMODE_READY		(3 << 4)
     45#define ATMEL_SMC_MODE_BAT_MASK			BIT(8)
     46#define ATMEL_SMC_MODE_BAT_SELECT		(0 << 8)
     47#define ATMEL_SMC_MODE_BAT_WRITE		(1 << 8)
     48#define ATMEL_SMC_MODE_DBW_MASK			GENMASK(13, 12)
     49#define ATMEL_SMC_MODE_DBW_8			(0 << 12)
     50#define ATMEL_SMC_MODE_DBW_16			(1 << 12)
     51#define ATMEL_SMC_MODE_DBW_32			(2 << 12)
     52#define ATMEL_SMC_MODE_TDF_MASK			GENMASK(19, 16)
     53#define ATMEL_SMC_MODE_TDF(x)			(((x) - 1) << 16)
     54#define ATMEL_SMC_MODE_TDF_MAX			16
     55#define ATMEL_SMC_MODE_TDF_MIN			1
     56#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED	BIT(20)
     57#define ATMEL_SMC_MODE_PMEN			BIT(24)
     58#define ATMEL_SMC_MODE_PS_MASK			GENMASK(29, 28)
     59#define ATMEL_SMC_MODE_PS_4			(0 << 28)
     60#define ATMEL_SMC_MODE_PS_8			(1 << 28)
     61#define ATMEL_SMC_MODE_PS_16			(2 << 28)
     62#define ATMEL_SMC_MODE_PS_32			(3 << 28)
     63
     64#define ATMEL_HSMC_TIMINGS(layout, cs)			\
     65	((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
     66#define ATMEL_HSMC_TIMINGS_OCMS			BIT(12)
     67#define ATMEL_HSMC_TIMINGS_RBNSEL(x)		((x) << 28)
     68#define ATMEL_HSMC_TIMINGS_NFSEL		BIT(31)
     69#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT		0
     70#define ATMEL_HSMC_TIMINGS_TADL_SHIFT		4
     71#define ATMEL_HSMC_TIMINGS_TAR_SHIFT		8
     72#define ATMEL_HSMC_TIMINGS_TRR_SHIFT		16
     73#define ATMEL_HSMC_TIMINGS_TWB_SHIFT		24
     74
     75struct atmel_hsmc_reg_layout {
     76	unsigned int timing_regs_offset;
     77};
     78
     79/**
     80 * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
     81 * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200)
     82 * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200)
     83 * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200)
     84 * @timings: advanced NAND related timings (only applicable to HSMC)
     85 * @mode: all kind of config parameters (see the fields definition above).
     86 *	  The mode fields are different on at91rm9200
     87 */
     88struct atmel_smc_cs_conf {
     89	u32 setup;
     90	u32 pulse;
     91	u32 cycle;
     92	u32 timings;
     93	u32 mode;
     94};
     95
     96void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
     97int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
     98				 unsigned int shift,
     99				 unsigned int ncycles);
    100int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
    101				unsigned int shift, unsigned int ncycles);
    102int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
    103				unsigned int shift, unsigned int ncycles);
    104int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
    105				unsigned int shift, unsigned int ncycles);
    106void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
    107			     const struct atmel_smc_cs_conf *conf);
    108void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
    109			      const struct atmel_hsmc_reg_layout *reglayout,
    110			      int cs, const struct atmel_smc_cs_conf *conf);
    111void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
    112			   struct atmel_smc_cs_conf *conf);
    113void atmel_hsmc_cs_conf_get(struct regmap *regmap,
    114			    const struct atmel_hsmc_reg_layout *reglayout,
    115			    int cs, struct atmel_smc_cs_conf *conf);
    116const struct atmel_hsmc_reg_layout *
    117atmel_hsmc_get_reg_layout(struct device_node *np);
    118
    119#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */