cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tmio.h (3894B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef MFD_TMIO_H
      3#define MFD_TMIO_H
      4
      5#include <linux/device.h>
      6#include <linux/fb.h>
      7#include <linux/io.h>
      8#include <linux/jiffies.h>
      9#include <linux/mmc/card.h>
     10#include <linux/platform_device.h>
     11#include <linux/pm_runtime.h>
     12
     13#define tmio_ioread8(addr) readb(addr)
     14#define tmio_ioread16(addr) readw(addr)
     15#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
     16#define tmio_ioread32(addr) \
     17	(((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
     18
     19#define tmio_iowrite8(val, addr) writeb((val), (addr))
     20#define tmio_iowrite16(val, addr) writew((val), (addr))
     21#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
     22#define tmio_iowrite32(val, addr) \
     23	do { \
     24		writew((val),       (addr)); \
     25		writew((val) >> 16, (addr) + 2); \
     26	} while (0)
     27
     28#define sd_config_write8(base, shift, reg, val) \
     29	tmio_iowrite8((val), (base) + ((reg) << (shift)))
     30#define sd_config_write16(base, shift, reg, val) \
     31	tmio_iowrite16((val), (base) + ((reg) << (shift)))
     32#define sd_config_write32(base, shift, reg, val) \
     33	do { \
     34		tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
     35		tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
     36	} while (0)
     37
     38/* tmio MMC platform flags */
     39/*
     40 * Some controllers can support a 2-byte block size when the bus width
     41 * is configured in 4-bit mode.
     42 */
     43#define TMIO_MMC_BLKSZ_2BYTES		BIT(1)
     44/*
     45 * Some controllers can support SDIO IRQ signalling.
     46 */
     47#define TMIO_MMC_SDIO_IRQ		BIT(2)
     48
     49/* Some features are only available or tested on R-Car Gen2 or later */
     50#define TMIO_MMC_MIN_RCAR2		BIT(3)
     51
     52/*
     53 * Some controllers require waiting for the SD bus to become
     54 * idle before writing to some registers.
     55 */
     56#define TMIO_MMC_HAS_IDLE_WAIT		BIT(4)
     57
     58/*
     59 * Use the busy timeout feature. Probably all TMIO versions support it. Yet,
     60 * we don't have documentation for old variants, so we enable only known good
     61 * variants with this flag. Can be removed once all variants are known good.
     62 */
     63#define TMIO_MMC_USE_BUSY_TIMEOUT	BIT(5)
     64
     65/*
     66 * Some controllers have CMD12 automatically
     67 * issue/non-issue register
     68 */
     69#define TMIO_MMC_HAVE_CMD12_CTRL	BIT(7)
     70
     71/* Controller has some SDIO status bits which must be 1 */
     72#define TMIO_MMC_SDIO_STATUS_SETBITS	BIT(8)
     73
     74/*
     75 * Some controllers have a 32-bit wide data port register
     76 */
     77#define TMIO_MMC_32BIT_DATA_PORT	BIT(9)
     78
     79/*
     80 * Some controllers allows to set SDx actual clock
     81 */
     82#define TMIO_MMC_CLK_ACTUAL		BIT(10)
     83
     84/* Some controllers have a CBSY bit */
     85#define TMIO_MMC_HAVE_CBSY		BIT(11)
     86
     87int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
     88int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
     89void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
     90void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
     91
     92struct dma_chan;
     93
     94/*
     95 * data for the MMC controller
     96 */
     97struct tmio_mmc_data {
     98	void				*chan_priv_tx;
     99	void				*chan_priv_rx;
    100	unsigned int			hclk;
    101	unsigned long			capabilities;
    102	unsigned long			capabilities2;
    103	unsigned long			flags;
    104	u32				ocr_mask;	/* available voltages */
    105	int				alignment_shift;
    106	dma_addr_t			dma_rx_offset;
    107	unsigned int			max_blk_count;
    108	unsigned short			max_segs;
    109	void (*set_pwr)(struct platform_device *host, int state);
    110	void (*set_clk_div)(struct platform_device *host, int state);
    111};
    112
    113/*
    114 * data for the NAND controller
    115 */
    116struct tmio_nand_data {
    117	struct nand_bbt_descr	*badblock_pattern;
    118	struct mtd_partition	*partition;
    119	unsigned int		num_partitions;
    120	const char *const	*part_parsers;
    121};
    122
    123#define FBIO_TMIO_ACC_WRITE	0x7C639300
    124#define FBIO_TMIO_ACC_SYNC	0x7C639301
    125
    126struct tmio_fb_data {
    127	int			(*lcd_set_power)(struct platform_device *fb_dev,
    128						 bool on);
    129	int			(*lcd_mode)(struct platform_device *fb_dev,
    130					    const struct fb_videomode *mode);
    131	int			num_modes;
    132	struct fb_videomode	*modes;
    133
    134	/* in mm: size of screen */
    135	int			height;
    136	int			width;
    137};
    138
    139#endif