tps65217.h (8436B)
1/* 2 * linux/mfd/tps65217.h 3 * 4 * Functions to access TPS65217 power management chip. 5 * 6 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation version 2. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#ifndef __LINUX_MFD_TPS65217_H 19#define __LINUX_MFD_TPS65217_H 20 21#include <linux/i2c.h> 22#include <linux/regulator/driver.h> 23#include <linux/regulator/machine.h> 24 25/* TPS chip id list */ 26#define TPS65217 0xF0 27 28/* I2C ID for TPS65217 part */ 29#define TPS65217_I2C_ID 0x24 30 31/* All register addresses */ 32#define TPS65217_REG_CHIPID 0X00 33#define TPS65217_REG_PPATH 0X01 34#define TPS65217_REG_INT 0X02 35#define TPS65217_REG_CHGCONFIG0 0X03 36#define TPS65217_REG_CHGCONFIG1 0X04 37#define TPS65217_REG_CHGCONFIG2 0X05 38#define TPS65217_REG_CHGCONFIG3 0X06 39#define TPS65217_REG_WLEDCTRL1 0X07 40#define TPS65217_REG_WLEDCTRL2 0X08 41#define TPS65217_REG_MUXCTRL 0X09 42#define TPS65217_REG_STATUS 0X0A 43#define TPS65217_REG_PASSWORD 0X0B 44#define TPS65217_REG_PGOOD 0X0C 45#define TPS65217_REG_DEFPG 0X0D 46#define TPS65217_REG_DEFDCDC1 0X0E 47#define TPS65217_REG_DEFDCDC2 0X0F 48#define TPS65217_REG_DEFDCDC3 0X10 49#define TPS65217_REG_DEFSLEW 0X11 50#define TPS65217_REG_DEFLDO1 0X12 51#define TPS65217_REG_DEFLDO2 0X13 52#define TPS65217_REG_DEFLS1 0X14 53#define TPS65217_REG_DEFLS2 0X15 54#define TPS65217_REG_ENABLE 0X16 55#define TPS65217_REG_DEFUVLO 0X18 56#define TPS65217_REG_SEQ1 0X19 57#define TPS65217_REG_SEQ2 0X1A 58#define TPS65217_REG_SEQ3 0X1B 59#define TPS65217_REG_SEQ4 0X1C 60#define TPS65217_REG_SEQ5 0X1D 61#define TPS65217_REG_SEQ6 0X1E 62 63#define TPS65217_REG_MAX TPS65217_REG_SEQ6 64 65/* Register field definitions */ 66#define TPS65217_CHIPID_CHIP_MASK 0xF0 67#define TPS65217_CHIPID_REV_MASK 0x0F 68 69#define TPS65217_PPATH_ACSINK_ENABLE BIT(7) 70#define TPS65217_PPATH_USBSINK_ENABLE BIT(6) 71#define TPS65217_PPATH_AC_PW_ENABLE BIT(5) 72#define TPS65217_PPATH_USB_PW_ENABLE BIT(4) 73#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C 74#define TPS65217_PPATH_USB_CURRENT_MASK 0x03 75 76#define TPS65217_INT_PBM BIT(6) 77#define TPS65217_INT_ACM BIT(5) 78#define TPS65217_INT_USBM BIT(4) 79#define TPS65217_INT_PBI BIT(2) 80#define TPS65217_INT_ACI BIT(1) 81#define TPS65217_INT_USBI BIT(0) 82#define TPS65217_INT_SHIFT 4 83#define TPS65217_INT_MASK (TPS65217_INT_PBM | TPS65217_INT_ACM | \ 84 TPS65217_INT_USBM) 85 86#define TPS65217_CHGCONFIG0_TREG BIT(7) 87#define TPS65217_CHGCONFIG0_DPPM BIT(6) 88#define TPS65217_CHGCONFIG0_TSUSP BIT(5) 89#define TPS65217_CHGCONFIG0_TERMI BIT(4) 90#define TPS65217_CHGCONFIG0_ACTIVE BIT(3) 91#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2) 92#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1) 93#define TPS65217_CHGCONFIG0_BATTEMP BIT(0) 94 95#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0 96#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5) 97#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4) 98#define TPS65217_CHGCONFIG1_RESET BIT(3) 99#define TPS65217_CHGCONFIG1_TERM BIT(2) 100#define TPS65217_CHGCONFIG1_SUSP BIT(1) 101#define TPS65217_CHGCONFIG1_CHG_EN BIT(0) 102 103#define TPS65217_CHGCONFIG2_DYNTMR BIT(7) 104#define TPS65217_CHGCONFIG2_VPREGHG BIT(6) 105#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30 106 107#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0 108#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30 109#define TPS65217_CHGCONFIG2_PCHRGT BIT(3) 110#define TPS65217_CHGCONFIG2_TERMIF 0x06 111#define TPS65217_CHGCONFIG2_TRANGE BIT(0) 112 113#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3) 114#define TPS65217_WLEDCTRL1_ISEL BIT(2) 115#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03 116 117#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F 118 119#define TPS65217_MUXCTRL_MUX_MASK 0x07 120 121#define TPS65217_STATUS_OFF BIT(7) 122#define TPS65217_STATUS_ACPWR BIT(3) 123#define TPS65217_STATUS_USBPWR BIT(2) 124#define TPS65217_STATUS_PB BIT(0) 125 126#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D 127 128#define TPS65217_PGOOD_LDO3_PG BIT(6) 129#define TPS65217_PGOOD_LDO4_PG BIT(5) 130#define TPS65217_PGOOD_DC1_PG BIT(4) 131#define TPS65217_PGOOD_DC2_PG BIT(3) 132#define TPS65217_PGOOD_DC3_PG BIT(2) 133#define TPS65217_PGOOD_LDO1_PG BIT(1) 134#define TPS65217_PGOOD_LDO2_PG BIT(0) 135 136#define TPS65217_DEFPG_LDO1PGM BIT(3) 137#define TPS65217_DEFPG_LDO2PGM BIT(2) 138#define TPS65217_DEFPG_PGDLY_MASK 0x03 139 140#define TPS65217_DEFDCDCX_XADJX BIT(7) 141#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F 142 143#define TPS65217_DEFSLEW_GO BIT(7) 144#define TPS65217_DEFSLEW_GODSBL BIT(6) 145#define TPS65217_DEFSLEW_PFM_EN1 BIT(5) 146#define TPS65217_DEFSLEW_PFM_EN2 BIT(4) 147#define TPS65217_DEFSLEW_PFM_EN3 BIT(3) 148#define TPS65217_DEFSLEW_SLEW_MASK 0x07 149 150#define TPS65217_DEFLDO1_LDO1_MASK 0x0F 151 152#define TPS65217_DEFLDO2_TRACK BIT(6) 153#define TPS65217_DEFLDO2_LDO2_MASK 0x3F 154 155#define TPS65217_DEFLDO3_LDO3_EN BIT(5) 156#define TPS65217_DEFLDO3_LDO3_MASK 0x1F 157 158#define TPS65217_DEFLDO4_LDO4_EN BIT(5) 159#define TPS65217_DEFLDO4_LDO4_MASK 0x1F 160 161#define TPS65217_ENABLE_LS1_EN BIT(6) 162#define TPS65217_ENABLE_LS2_EN BIT(5) 163#define TPS65217_ENABLE_DC1_EN BIT(4) 164#define TPS65217_ENABLE_DC2_EN BIT(3) 165#define TPS65217_ENABLE_DC3_EN BIT(2) 166#define TPS65217_ENABLE_LDO1_EN BIT(1) 167#define TPS65217_ENABLE_LDO2_EN BIT(0) 168 169#define TPS65217_DEFUVLO_UVLOHYS BIT(2) 170#define TPS65217_DEFUVLO_UVLO_MASK 0x03 171 172#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0 173#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F 174 175#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0 176#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F 177 178#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0 179#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F 180 181#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0 182 183#define TPS65217_SEQ5_DLY1_MASK 0xC0 184#define TPS65217_SEQ5_DLY2_MASK 0x30 185#define TPS65217_SEQ5_DLY3_MASK 0x0C 186#define TPS65217_SEQ5_DLY4_MASK 0x03 187 188#define TPS65217_SEQ6_DLY5_MASK 0xC0 189#define TPS65217_SEQ6_DLY6_MASK 0x30 190#define TPS65217_SEQ6_SEQUP BIT(2) 191#define TPS65217_SEQ6_SEQDWN BIT(1) 192#define TPS65217_SEQ6_INSTDWN BIT(0) 193 194#define TPS65217_MAX_REGISTER 0x1E 195#define TPS65217_PROTECT_NONE 0 196#define TPS65217_PROTECT_L1 1 197#define TPS65217_PROTECT_L2 2 198 199 200enum tps65217_regulator_id { 201 /* DCDC's */ 202 TPS65217_DCDC_1, 203 TPS65217_DCDC_2, 204 TPS65217_DCDC_3, 205 /* LDOs */ 206 TPS65217_LDO_1, 207 TPS65217_LDO_2, 208 TPS65217_LDO_3, 209 TPS65217_LDO_4, 210}; 211 212#define TPS65217_MAX_REG_ID TPS65217_LDO_4 213 214/* Number of step-down converters available */ 215#define TPS65217_NUM_DCDC 3 216/* Number of LDO voltage regulators available */ 217#define TPS65217_NUM_LDO 4 218/* Number of total regulators available */ 219#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO) 220 221enum tps65217_bl_isel { 222 TPS65217_BL_ISET1 = 1, 223 TPS65217_BL_ISET2, 224}; 225 226enum tps65217_bl_fdim { 227 TPS65217_BL_FDIM_100HZ, 228 TPS65217_BL_FDIM_200HZ, 229 TPS65217_BL_FDIM_500HZ, 230 TPS65217_BL_FDIM_1000HZ, 231}; 232 233struct tps65217_bl_pdata { 234 enum tps65217_bl_isel isel; 235 enum tps65217_bl_fdim fdim; 236 int dft_brightness; 237}; 238 239/* Interrupt numbers */ 240#define TPS65217_IRQ_USB 0 241#define TPS65217_IRQ_AC 1 242#define TPS65217_IRQ_PB 2 243#define TPS65217_NUM_IRQ 3 244 245/** 246 * struct tps65217_board - packages regulator init data 247 * @tps65217_regulator_data: regulator initialization values 248 * 249 * Board data may be used to initialize regulator. 250 */ 251struct tps65217_board { 252 struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR]; 253 struct device_node *of_node[TPS65217_NUM_REGULATOR]; 254 struct tps65217_bl_pdata *bl_pdata; 255}; 256 257/** 258 * struct tps65217 - tps65217 sub-driver chip access routines 259 * 260 * Device data may be used to access the TPS65217 chip 261 */ 262 263struct tps65217 { 264 struct device *dev; 265 struct tps65217_board *pdata; 266 struct regulator_desc desc[TPS65217_NUM_REGULATOR]; 267 struct regmap *regmap; 268 u8 *strobes; 269 struct irq_domain *irq_domain; 270 struct mutex irq_lock; 271 u8 irq_mask; 272 int irq; 273}; 274 275static inline struct tps65217 *dev_to_tps65217(struct device *dev) 276{ 277 return dev_get_drvdata(dev); 278} 279 280int tps65217_reg_read(struct tps65217 *tps, unsigned int reg, 281 unsigned int *val); 282int tps65217_reg_write(struct tps65217 *tps, unsigned int reg, 283 unsigned int val, unsigned int level); 284int tps65217_set_bits(struct tps65217 *tps, unsigned int reg, 285 unsigned int mask, unsigned int val, unsigned int level); 286int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg, 287 unsigned int mask, unsigned int level); 288 289#endif /* __LINUX_MFD_TPS65217_H */