tps65912.h (10146B)
1/* 2 * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/ 3 * Andrew F. Davis <afd@ti.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * kind, whether expressed or implied; without even the implied warranty 11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License version 2 for more details. 13 * 14 * Based on the TPS65218 driver and the previous TPS65912 driver by 15 * Margarita Olaya Cabrera <magi@slimlogic.co.uk> 16 */ 17 18#ifndef __LINUX_MFD_TPS65912_H 19#define __LINUX_MFD_TPS65912_H 20 21#include <linux/device.h> 22#include <linux/regmap.h> 23 24/* List of registers for TPS65912 */ 25#define TPS65912_DCDC1_CTRL 0x00 26#define TPS65912_DCDC2_CTRL 0x01 27#define TPS65912_DCDC3_CTRL 0x02 28#define TPS65912_DCDC4_CTRL 0x03 29#define TPS65912_DCDC1_OP 0x04 30#define TPS65912_DCDC1_AVS 0x05 31#define TPS65912_DCDC1_LIMIT 0x06 32#define TPS65912_DCDC2_OP 0x07 33#define TPS65912_DCDC2_AVS 0x08 34#define TPS65912_DCDC2_LIMIT 0x09 35#define TPS65912_DCDC3_OP 0x0A 36#define TPS65912_DCDC3_AVS 0x0B 37#define TPS65912_DCDC3_LIMIT 0x0C 38#define TPS65912_DCDC4_OP 0x0D 39#define TPS65912_DCDC4_AVS 0x0E 40#define TPS65912_DCDC4_LIMIT 0x0F 41#define TPS65912_LDO1_OP 0x10 42#define TPS65912_LDO1_AVS 0x11 43#define TPS65912_LDO1_LIMIT 0x12 44#define TPS65912_LDO2_OP 0x13 45#define TPS65912_LDO2_AVS 0x14 46#define TPS65912_LDO2_LIMIT 0x15 47#define TPS65912_LDO3_OP 0x16 48#define TPS65912_LDO3_AVS 0x17 49#define TPS65912_LDO3_LIMIT 0x18 50#define TPS65912_LDO4_OP 0x19 51#define TPS65912_LDO4_AVS 0x1A 52#define TPS65912_LDO4_LIMIT 0x1B 53#define TPS65912_LDO5 0x1C 54#define TPS65912_LDO6 0x1D 55#define TPS65912_LDO7 0x1E 56#define TPS65912_LDO8 0x1F 57#define TPS65912_LDO9 0x20 58#define TPS65912_LDO10 0x21 59#define TPS65912_THRM 0x22 60#define TPS65912_CLK32OUT 0x23 61#define TPS65912_DEVCTRL 0x24 62#define TPS65912_DEVCTRL2 0x25 63#define TPS65912_I2C_SPI_CFG 0x26 64#define TPS65912_KEEP_ON 0x27 65#define TPS65912_KEEP_ON2 0x28 66#define TPS65912_SET_OFF1 0x29 67#define TPS65912_SET_OFF2 0x2A 68#define TPS65912_DEF_VOLT 0x2B 69#define TPS65912_DEF_VOLT_MAPPING 0x2C 70#define TPS65912_DISCHARGE 0x2D 71#define TPS65912_DISCHARGE2 0x2E 72#define TPS65912_EN1_SET1 0x2F 73#define TPS65912_EN1_SET2 0x30 74#define TPS65912_EN2_SET1 0x31 75#define TPS65912_EN2_SET2 0x32 76#define TPS65912_EN3_SET1 0x33 77#define TPS65912_EN3_SET2 0x34 78#define TPS65912_EN4_SET1 0x35 79#define TPS65912_EN4_SET2 0x36 80#define TPS65912_PGOOD 0x37 81#define TPS65912_PGOOD2 0x38 82#define TPS65912_INT_STS 0x39 83#define TPS65912_INT_MSK 0x3A 84#define TPS65912_INT_STS2 0x3B 85#define TPS65912_INT_MSK2 0x3C 86#define TPS65912_INT_STS3 0x3D 87#define TPS65912_INT_MSK3 0x3E 88#define TPS65912_INT_STS4 0x3F 89#define TPS65912_INT_MSK4 0x40 90#define TPS65912_GPIO1 0x41 91#define TPS65912_GPIO2 0x42 92#define TPS65912_GPIO3 0x43 93#define TPS65912_GPIO4 0x44 94#define TPS65912_GPIO5 0x45 95#define TPS65912_VMON 0x46 96#define TPS65912_LEDA_CTRL1 0x47 97#define TPS65912_LEDA_CTRL2 0x48 98#define TPS65912_LEDA_CTRL3 0x49 99#define TPS65912_LEDA_CTRL4 0x4A 100#define TPS65912_LEDA_CTRL5 0x4B 101#define TPS65912_LEDA_CTRL6 0x4C 102#define TPS65912_LEDA_CTRL7 0x4D 103#define TPS65912_LEDA_CTRL8 0x4E 104#define TPS65912_LEDB_CTRL1 0x4F 105#define TPS65912_LEDB_CTRL2 0x50 106#define TPS65912_LEDB_CTRL3 0x51 107#define TPS65912_LEDB_CTRL4 0x52 108#define TPS65912_LEDB_CTRL5 0x53 109#define TPS65912_LEDB_CTRL6 0x54 110#define TPS65912_LEDB_CTRL7 0x55 111#define TPS65912_LEDB_CTRL8 0x56 112#define TPS65912_LEDC_CTRL1 0x57 113#define TPS65912_LEDC_CTRL2 0x58 114#define TPS65912_LEDC_CTRL3 0x59 115#define TPS65912_LEDC_CTRL4 0x5A 116#define TPS65912_LEDC_CTRL5 0x5B 117#define TPS65912_LEDC_CTRL6 0x5C 118#define TPS65912_LEDC_CTRL7 0x5D 119#define TPS65912_LEDC_CTRL8 0x5E 120#define TPS65912_LED_RAMP_UP_TIME 0x5F 121#define TPS65912_LED_RAMP_DOWN_TIME 0x60 122#define TPS65912_LED_SEQ_EN 0x61 123#define TPS65912_LOADSWITCH 0x62 124#define TPS65912_SPARE 0x63 125#define TPS65912_VERNUM 0x64 126#define TPS6591X_MAX_REGISTER 0x64 127 128/* INT_STS Register field definitions */ 129#define TPS65912_INT_STS_PWRHOLD_F BIT(0) 130#define TPS65912_INT_STS_VMON BIT(1) 131#define TPS65912_INT_STS_PWRON BIT(2) 132#define TPS65912_INT_STS_PWRON_LP BIT(3) 133#define TPS65912_INT_STS_PWRHOLD_R BIT(4) 134#define TPS65912_INT_STS_HOTDIE BIT(5) 135#define TPS65912_INT_STS_GPIO1_R BIT(6) 136#define TPS65912_INT_STS_GPIO1_F BIT(7) 137 138/* INT_STS Register field definitions */ 139#define TPS65912_INT_STS2_GPIO2_R BIT(0) 140#define TPS65912_INT_STS2_GPIO2_F BIT(1) 141#define TPS65912_INT_STS2_GPIO3_R BIT(2) 142#define TPS65912_INT_STS2_GPIO3_F BIT(3) 143#define TPS65912_INT_STS2_GPIO4_R BIT(4) 144#define TPS65912_INT_STS2_GPIO4_F BIT(5) 145#define TPS65912_INT_STS2_GPIO5_R BIT(6) 146#define TPS65912_INT_STS2_GPIO5_F BIT(7) 147 148/* INT_STS Register field definitions */ 149#define TPS65912_INT_STS3_PGOOD_DCDC1 BIT(0) 150#define TPS65912_INT_STS3_PGOOD_DCDC2 BIT(1) 151#define TPS65912_INT_STS3_PGOOD_DCDC3 BIT(2) 152#define TPS65912_INT_STS3_PGOOD_DCDC4 BIT(3) 153#define TPS65912_INT_STS3_PGOOD_LDO1 BIT(4) 154#define TPS65912_INT_STS3_PGOOD_LDO2 BIT(5) 155#define TPS65912_INT_STS3_PGOOD_LDO3 BIT(6) 156#define TPS65912_INT_STS3_PGOOD_LDO4 BIT(7) 157 158/* INT_STS Register field definitions */ 159#define TPS65912_INT_STS4_PGOOD_LDO5 BIT(0) 160#define TPS65912_INT_STS4_PGOOD_LDO6 BIT(1) 161#define TPS65912_INT_STS4_PGOOD_LDO7 BIT(2) 162#define TPS65912_INT_STS4_PGOOD_LDO8 BIT(3) 163#define TPS65912_INT_STS4_PGOOD_LDO9 BIT(4) 164#define TPS65912_INT_STS4_PGOOD_LDO10 BIT(5) 165 166/* GPIO 1 and 2 Register field definitions */ 167#define GPIO_SLEEP_MASK 0x80 168#define GPIO_SLEEP_SHIFT 7 169#define GPIO_DEB_MASK 0x10 170#define GPIO_DEB_SHIFT 4 171#define GPIO_CFG_MASK 0x04 172#define GPIO_CFG_SHIFT 2 173#define GPIO_STS_MASK 0x02 174#define GPIO_STS_SHIFT 1 175#define GPIO_SET_MASK 0x01 176#define GPIO_SET_SHIFT 0 177 178/* GPIO 3 Register field definitions */ 179#define GPIO3_SLEEP_MASK 0x80 180#define GPIO3_SLEEP_SHIFT 7 181#define GPIO3_SEL_MASK 0x40 182#define GPIO3_SEL_SHIFT 6 183#define GPIO3_ODEN_MASK 0x20 184#define GPIO3_ODEN_SHIFT 5 185#define GPIO3_DEB_MASK 0x10 186#define GPIO3_DEB_SHIFT 4 187#define GPIO3_PDEN_MASK 0x08 188#define GPIO3_PDEN_SHIFT 3 189#define GPIO3_CFG_MASK 0x04 190#define GPIO3_CFG_SHIFT 2 191#define GPIO3_STS_MASK 0x02 192#define GPIO3_STS_SHIFT 1 193#define GPIO3_SET_MASK 0x01 194#define GPIO3_SET_SHIFT 0 195 196/* GPIO 4 Register field definitions */ 197#define GPIO4_SLEEP_MASK 0x80 198#define GPIO4_SLEEP_SHIFT 7 199#define GPIO4_SEL_MASK 0x40 200#define GPIO4_SEL_SHIFT 6 201#define GPIO4_ODEN_MASK 0x20 202#define GPIO4_ODEN_SHIFT 5 203#define GPIO4_DEB_MASK 0x10 204#define GPIO4_DEB_SHIFT 4 205#define GPIO4_PDEN_MASK 0x08 206#define GPIO4_PDEN_SHIFT 3 207#define GPIO4_CFG_MASK 0x04 208#define GPIO4_CFG_SHIFT 2 209#define GPIO4_STS_MASK 0x02 210#define GPIO4_STS_SHIFT 1 211#define GPIO4_SET_MASK 0x01 212#define GPIO4_SET_SHIFT 0 213 214/* Register THERM (0x80) register.RegisterDescription */ 215#define THERM_THERM_HD_MASK 0x20 216#define THERM_THERM_HD_SHIFT 5 217#define THERM_THERM_TS_MASK 0x10 218#define THERM_THERM_TS_SHIFT 4 219#define THERM_THERM_HDSEL_MASK 0x0C 220#define THERM_THERM_HDSEL_SHIFT 2 221#define THERM_RSVD1_MASK 0x02 222#define THERM_RSVD1_SHIFT 1 223#define THERM_THERM_STATE_MASK 0x01 224#define THERM_THERM_STATE_SHIFT 0 225 226/* Register DCDCCTRL1 register.RegisterDescription */ 227#define DCDCCTRL_VCON_ENABLE_MASK 0x80 228#define DCDCCTRL_VCON_ENABLE_SHIFT 7 229#define DCDCCTRL_VCON_RANGE1_MASK 0x40 230#define DCDCCTRL_VCON_RANGE1_SHIFT 6 231#define DCDCCTRL_VCON_RANGE0_MASK 0x20 232#define DCDCCTRL_VCON_RANGE0_SHIFT 5 233#define DCDCCTRL_TSTEP2_MASK 0x10 234#define DCDCCTRL_TSTEP2_SHIFT 4 235#define DCDCCTRL_TSTEP1_MASK 0x08 236#define DCDCCTRL_TSTEP1_SHIFT 3 237#define DCDCCTRL_TSTEP0_MASK 0x04 238#define DCDCCTRL_TSTEP0_SHIFT 2 239#define DCDCCTRL_DCDC1_MODE_MASK 0x02 240#define DCDCCTRL_DCDC1_MODE_SHIFT 1 241 242/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */ 243#define DCDCCTRL_TSTEP2_MASK 0x10 244#define DCDCCTRL_TSTEP2_SHIFT 4 245#define DCDCCTRL_TSTEP1_MASK 0x08 246#define DCDCCTRL_TSTEP1_SHIFT 3 247#define DCDCCTRL_TSTEP0_MASK 0x04 248#define DCDCCTRL_TSTEP0_SHIFT 2 249#define DCDCCTRL_DCDC_MODE_MASK 0x02 250#define DCDCCTRL_DCDC_MODE_SHIFT 1 251#define DCDCCTRL_RSVD0_MASK 0x01 252#define DCDCCTRL_RSVD0_SHIFT 0 253 254/* Register DCDCCTRL4 register.RegisterDescription */ 255#define DCDCCTRL_RAMP_TIME_MASK 0x01 256#define DCDCCTRL_RAMP_TIME_SHIFT 0 257 258/* Register DCDCx_AVS */ 259#define DCDC_AVS_ENABLE_MASK 0x80 260#define DCDC_AVS_ENABLE_SHIFT 7 261#define DCDC_AVS_ECO_MASK 0x40 262#define DCDC_AVS_ECO_SHIFT 6 263 264/* Register DCDCx_LIMIT */ 265#define DCDC_LIMIT_RANGE_MASK 0xC0 266#define DCDC_LIMIT_RANGE_SHIFT 6 267#define DCDC_LIMIT_MAX_SEL_MASK 0x3F 268#define DCDC_LIMIT_MAX_SEL_SHIFT 0 269 270/* Define the TPS65912 IRQ numbers */ 271enum tps65912_irqs { 272 /* INT_STS registers */ 273 TPS65912_IRQ_PWRHOLD_F, 274 TPS65912_IRQ_VMON, 275 TPS65912_IRQ_PWRON, 276 TPS65912_IRQ_PWRON_LP, 277 TPS65912_IRQ_PWRHOLD_R, 278 TPS65912_IRQ_HOTDIE, 279 TPS65912_IRQ_GPIO1_R, 280 TPS65912_IRQ_GPIO1_F, 281 /* INT_STS2 registers */ 282 TPS65912_IRQ_GPIO2_R, 283 TPS65912_IRQ_GPIO2_F, 284 TPS65912_IRQ_GPIO3_R, 285 TPS65912_IRQ_GPIO3_F, 286 TPS65912_IRQ_GPIO4_R, 287 TPS65912_IRQ_GPIO4_F, 288 TPS65912_IRQ_GPIO5_R, 289 TPS65912_IRQ_GPIO5_F, 290 /* INT_STS3 registers */ 291 TPS65912_IRQ_PGOOD_DCDC1, 292 TPS65912_IRQ_PGOOD_DCDC2, 293 TPS65912_IRQ_PGOOD_DCDC3, 294 TPS65912_IRQ_PGOOD_DCDC4, 295 TPS65912_IRQ_PGOOD_LDO1, 296 TPS65912_IRQ_PGOOD_LDO2, 297 TPS65912_IRQ_PGOOD_LDO3, 298 TPS65912_IRQ_PGOOD_LDO4, 299 /* INT_STS4 registers */ 300 TPS65912_IRQ_PGOOD_LDO5, 301 TPS65912_IRQ_PGOOD_LDO6, 302 TPS65912_IRQ_PGOOD_LDO7, 303 TPS65912_IRQ_PGOOD_LDO8, 304 TPS65912_IRQ_PGOOD_LDO9, 305 TPS65912_IRQ_PGOOD_LDO10, 306}; 307 308/* 309 * struct tps65912 - state holder for the tps65912 driver 310 * 311 * Device data may be used to access the TPS65912 chip 312 */ 313struct tps65912 { 314 struct device *dev; 315 struct regmap *regmap; 316 317 /* IRQ Data */ 318 int irq; 319 struct regmap_irq_chip_data *irq_data; 320}; 321 322extern const struct regmap_config tps65912_regmap_config; 323 324int tps65912_device_init(struct tps65912 *tps); 325void tps65912_device_exit(struct tps65912 *tps); 326 327#endif /* __LINUX_MFD_TPS65912_H */