cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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device.h (42819B)


      1/*
      2 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
      3 *
      4 * This software is available to you under a choice of one of two
      5 * licenses.  You may choose to be licensed under the terms of the GNU
      6 * General Public License (GPL) Version 2, available from the file
      7 * COPYING in the main directory of this source tree, or the
      8 * OpenIB.org BSD license below:
      9 *
     10 *     Redistribution and use in source and binary forms, with or
     11 *     without modification, are permitted provided that the following
     12 *     conditions are met:
     13 *
     14 *	- Redistributions of source code must retain the above
     15 *	  copyright notice, this list of conditions and the following
     16 *	  disclaimer.
     17 *
     18 *	- Redistributions in binary form must reproduce the above
     19 *	  copyright notice, this list of conditions and the following
     20 *	  disclaimer in the documentation and/or other materials
     21 *	  provided with the distribution.
     22 *
     23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     30 * SOFTWARE.
     31 */
     32
     33#ifndef MLX4_DEVICE_H
     34#define MLX4_DEVICE_H
     35
     36#include <linux/if_ether.h>
     37#include <linux/pci.h>
     38#include <linux/completion.h>
     39#include <linux/radix-tree.h>
     40#include <linux/cpu_rmap.h>
     41#include <linux/crash_dump.h>
     42
     43#include <linux/refcount.h>
     44
     45#include <linux/timecounter.h>
     46
     47#define DEFAULT_UAR_PAGE_SHIFT  12
     48
     49#define MAX_MSIX		128
     50#define MIN_MSIX_P_PORT		5
     51#define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
     52					 (dev_cap).num_ports * MIN_MSIX_P_PORT)
     53
     54#define MLX4_MAX_100M_UNITS_VAL		255	/*
     55						 * work around: can't set values
     56						 * greater then this value when
     57						 * using 100 Mbps units.
     58						 */
     59#define MLX4_RATELIMIT_100M_UNITS	3	/* 100 Mbps */
     60#define MLX4_RATELIMIT_1G_UNITS		4	/* 1 Gbps */
     61#define MLX4_RATELIMIT_DEFAULT		0x00ff
     62
     63#define MLX4_ROCE_MAX_GIDS	128
     64#define MLX4_ROCE_PF_GIDS	16
     65
     66enum {
     67	MLX4_FLAG_MSI_X		= 1 << 0,
     68	MLX4_FLAG_OLD_PORT_CMDS	= 1 << 1,
     69	MLX4_FLAG_MASTER	= 1 << 2,
     70	MLX4_FLAG_SLAVE		= 1 << 3,
     71	MLX4_FLAG_SRIOV		= 1 << 4,
     72	MLX4_FLAG_OLD_REG_MAC	= 1 << 6,
     73	MLX4_FLAG_BONDED	= 1 << 7,
     74	MLX4_FLAG_SECURE_HOST	= 1 << 8,
     75};
     76
     77enum {
     78	MLX4_PORT_CAP_IS_SM	= 1 << 1,
     79	MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
     80};
     81
     82enum {
     83	MLX4_MAX_PORTS		= 2,
     84	MLX4_MAX_PORT_PKEYS	= 128,
     85	MLX4_MAX_PORT_GIDS	= 128
     86};
     87
     88/* base qkey for use in sriov tunnel-qp/proxy-qp communication.
     89 * These qkeys must not be allowed for general use. This is a 64k range,
     90 * and to test for violation, we use the mask (protect against future chg).
     91 */
     92#define MLX4_RESERVED_QKEY_BASE  (0xFFFF0000)
     93#define MLX4_RESERVED_QKEY_MASK  (0xFFFF0000)
     94
     95enum {
     96	MLX4_BOARD_ID_LEN = 64
     97};
     98
     99enum {
    100	MLX4_MAX_NUM_PF		= 16,
    101	MLX4_MAX_NUM_VF		= 126,
    102	MLX4_MAX_NUM_VF_P_PORT  = 64,
    103	MLX4_MFUNC_MAX		= 128,
    104	MLX4_MAX_EQ_NUM		= 1024,
    105	MLX4_MFUNC_EQ_NUM	= 4,
    106	MLX4_MFUNC_MAX_EQES     = 8,
    107	MLX4_MFUNC_EQE_MASK     = (MLX4_MFUNC_MAX_EQES - 1)
    108};
    109
    110/* Driver supports 3 different device methods to manage traffic steering:
    111 *	-device managed - High level API for ib and eth flow steering. FW is
    112 *			  managing flow steering tables.
    113 *	- B0 steering mode - Common low level API for ib and (if supported) eth.
    114 *	- A0 steering mode - Limited low level API for eth. In case of IB,
    115 *			     B0 mode is in use.
    116 */
    117enum {
    118	MLX4_STEERING_MODE_A0,
    119	MLX4_STEERING_MODE_B0,
    120	MLX4_STEERING_MODE_DEVICE_MANAGED
    121};
    122
    123enum {
    124	MLX4_STEERING_DMFS_A0_DEFAULT,
    125	MLX4_STEERING_DMFS_A0_DYNAMIC,
    126	MLX4_STEERING_DMFS_A0_STATIC,
    127	MLX4_STEERING_DMFS_A0_DISABLE,
    128	MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
    129};
    130
    131static inline const char *mlx4_steering_mode_str(int steering_mode)
    132{
    133	switch (steering_mode) {
    134	case MLX4_STEERING_MODE_A0:
    135		return "A0 steering";
    136
    137	case MLX4_STEERING_MODE_B0:
    138		return "B0 steering";
    139
    140	case MLX4_STEERING_MODE_DEVICE_MANAGED:
    141		return "Device managed flow steering";
    142
    143	default:
    144		return "Unrecognize steering mode";
    145	}
    146}
    147
    148enum {
    149	MLX4_TUNNEL_OFFLOAD_MODE_NONE,
    150	MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
    151};
    152
    153enum {
    154	MLX4_DEV_CAP_FLAG_RC		= 1LL <<  0,
    155	MLX4_DEV_CAP_FLAG_UC		= 1LL <<  1,
    156	MLX4_DEV_CAP_FLAG_UD		= 1LL <<  2,
    157	MLX4_DEV_CAP_FLAG_XRC		= 1LL <<  3,
    158	MLX4_DEV_CAP_FLAG_SRQ		= 1LL <<  6,
    159	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1LL <<  7,
    160	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1LL <<  8,
    161	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1LL <<  9,
    162	MLX4_DEV_CAP_FLAG_DPDP		= 1LL << 12,
    163	MLX4_DEV_CAP_FLAG_BLH		= 1LL << 15,
    164	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1LL << 16,
    165	MLX4_DEV_CAP_FLAG_APM		= 1LL << 17,
    166	MLX4_DEV_CAP_FLAG_ATOMIC	= 1LL << 18,
    167	MLX4_DEV_CAP_FLAG_RAW_MCAST	= 1LL << 19,
    168	MLX4_DEV_CAP_FLAG_UD_AV_PORT	= 1LL << 20,
    169	MLX4_DEV_CAP_FLAG_UD_MCAST	= 1LL << 21,
    170	MLX4_DEV_CAP_FLAG_IBOE		= 1LL << 30,
    171	MLX4_DEV_CAP_FLAG_UC_LOOPBACK	= 1LL << 32,
    172	MLX4_DEV_CAP_FLAG_FCS_KEEP	= 1LL << 34,
    173	MLX4_DEV_CAP_FLAG_WOL_PORT1	= 1LL << 37,
    174	MLX4_DEV_CAP_FLAG_WOL_PORT2	= 1LL << 38,
    175	MLX4_DEV_CAP_FLAG_UDP_RSS	= 1LL << 40,
    176	MLX4_DEV_CAP_FLAG_VEP_UC_STEER	= 1LL << 41,
    177	MLX4_DEV_CAP_FLAG_VEP_MC_STEER	= 1LL << 42,
    178	MLX4_DEV_CAP_FLAG_COUNTERS	= 1LL << 48,
    179	MLX4_DEV_CAP_FLAG_RSS_IP_FRAG   = 1LL << 52,
    180	MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
    181	MLX4_DEV_CAP_FLAG_SENSE_SUPPORT	= 1LL << 55,
    182	MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
    183	MLX4_DEV_CAP_FLAG_64B_EQE	= 1LL << 61,
    184	MLX4_DEV_CAP_FLAG_64B_CQE	= 1LL << 62
    185};
    186
    187enum {
    188	MLX4_DEV_CAP_FLAG2_RSS			= 1LL <<  0,
    189	MLX4_DEV_CAP_FLAG2_RSS_TOP		= 1LL <<  1,
    190	MLX4_DEV_CAP_FLAG2_RSS_XOR		= 1LL <<  2,
    191	MLX4_DEV_CAP_FLAG2_FS_EN		= 1LL <<  3,
    192	MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN	= 1LL <<  4,
    193	MLX4_DEV_CAP_FLAG2_TS			= 1LL <<  5,
    194	MLX4_DEV_CAP_FLAG2_VLAN_CONTROL		= 1LL <<  6,
    195	MLX4_DEV_CAP_FLAG2_FSM			= 1LL <<  7,
    196	MLX4_DEV_CAP_FLAG2_UPDATE_QP		= 1LL <<  8,
    197	MLX4_DEV_CAP_FLAG2_DMFS_IPOIB		= 1LL <<  9,
    198	MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS	= 1LL <<  10,
    199	MLX4_DEV_CAP_FLAG2_MAD_DEMUX		= 1LL <<  11,
    200	MLX4_DEV_CAP_FLAG2_CQE_STRIDE		= 1LL <<  12,
    201	MLX4_DEV_CAP_FLAG2_EQE_STRIDE		= 1LL <<  13,
    202	MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL        = 1LL <<  14,
    203	MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP	= 1LL <<  15,
    204	MLX4_DEV_CAP_FLAG2_CONFIG_DEV		= 1LL <<  16,
    205	MLX4_DEV_CAP_FLAG2_SYS_EQS		= 1LL <<  17,
    206	MLX4_DEV_CAP_FLAG2_80_VFS		= 1LL <<  18,
    207	MLX4_DEV_CAP_FLAG2_FS_A0		= 1LL <<  19,
    208	MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
    209	MLX4_DEV_CAP_FLAG2_PORT_REMAP		= 1LL <<  21,
    210	MLX4_DEV_CAP_FLAG2_QCN			= 1LL <<  22,
    211	MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT	= 1LL <<  23,
    212	MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN         = 1LL <<  24,
    213	MLX4_DEV_CAP_FLAG2_QOS_VPP		= 1LL <<  25,
    214	MLX4_DEV_CAP_FLAG2_ETS_CFG		= 1LL <<  26,
    215	MLX4_DEV_CAP_FLAG2_PORT_BEACON		= 1LL <<  27,
    216	MLX4_DEV_CAP_FLAG2_IGNORE_FCS		= 1LL <<  28,
    217	MLX4_DEV_CAP_FLAG2_PHV_EN		= 1LL <<  29,
    218	MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN	= 1LL <<  30,
    219	MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
    220	MLX4_DEV_CAP_FLAG2_LB_SRC_CHK           = 1ULL << 32,
    221	MLX4_DEV_CAP_FLAG2_ROCE_V1_V2		= 1ULL <<  33,
    222	MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER   = 1ULL <<  34,
    223	MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT	= 1ULL <<  35,
    224	MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP          = 1ULL <<  36,
    225	MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37,
    226	MLX4_DEV_CAP_FLAG2_USER_MAC_EN		= 1ULL << 38,
    227	MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1ULL << 39,
    228	MLX4_DEV_CAP_FLAG2_SW_CQ_INIT           = 1ULL << 40,
    229};
    230
    231enum {
    232	MLX4_QUERY_FUNC_FLAGS_BF_RES_QP		= 1LL << 0,
    233	MLX4_QUERY_FUNC_FLAGS_A0_RES_QP		= 1LL << 1
    234};
    235
    236enum {
    237	MLX4_VF_CAP_FLAG_RESET			= 1 << 0
    238};
    239
    240/* bit enums for an 8-bit flags field indicating special use
    241 * QPs which require special handling in qp_reserve_range.
    242 * Currently, this only includes QPs used by the ETH interface,
    243 * where we expect to use blueflame.  These QPs must not have
    244 * bits 6 and 7 set in their qp number.
    245 *
    246 * This enum may use only bits 0..7.
    247 */
    248enum {
    249	MLX4_RESERVE_A0_QP	= 1 << 6,
    250	MLX4_RESERVE_ETH_BF_QP	= 1 << 7,
    251};
    252
    253enum {
    254	MLX4_DEV_CAP_64B_EQE_ENABLED	= 1LL << 0,
    255	MLX4_DEV_CAP_64B_CQE_ENABLED	= 1LL << 1,
    256	MLX4_DEV_CAP_CQE_STRIDE_ENABLED	= 1LL << 2,
    257	MLX4_DEV_CAP_EQE_STRIDE_ENABLED	= 1LL << 3
    258};
    259
    260enum {
    261	MLX4_FUNC_CAP_64B_EQE_CQE	= 1L << 0,
    262	MLX4_FUNC_CAP_EQE_CQE_STRIDE	= 1L << 1,
    263	MLX4_FUNC_CAP_DMFS_A0_STATIC	= 1L << 2
    264};
    265
    266
    267#define MLX4_ATTR_EXTENDED_PORT_INFO	cpu_to_be16(0xff90)
    268
    269enum {
    270	MLX4_BMME_FLAG_WIN_TYPE_2B	= 1 <<  1,
    271	MLX4_BMME_FLAG_LOCAL_INV	= 1 <<  6,
    272	MLX4_BMME_FLAG_REMOTE_INV	= 1 <<  7,
    273	MLX4_BMME_FLAG_TYPE_2_WIN	= 1 <<  9,
    274	MLX4_BMME_FLAG_RESERVED_LKEY	= 1 << 10,
    275	MLX4_BMME_FLAG_FAST_REG_WR	= 1 << 11,
    276	MLX4_BMME_FLAG_ROCE_V1_V2	= 1 << 19,
    277	MLX4_BMME_FLAG_PORT_REMAP	= 1 << 24,
    278	MLX4_BMME_FLAG_VSD_INIT2RTR	= 1 << 28,
    279};
    280
    281enum {
    282	MLX4_FLAG_PORT_REMAP		= MLX4_BMME_FLAG_PORT_REMAP,
    283	MLX4_FLAG_ROCE_V1_V2		= MLX4_BMME_FLAG_ROCE_V1_V2
    284};
    285
    286enum mlx4_event {
    287	MLX4_EVENT_TYPE_COMP		   = 0x00,
    288	MLX4_EVENT_TYPE_PATH_MIG	   = 0x01,
    289	MLX4_EVENT_TYPE_COMM_EST	   = 0x02,
    290	MLX4_EVENT_TYPE_SQ_DRAINED	   = 0x03,
    291	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE	   = 0x13,
    292	MLX4_EVENT_TYPE_SRQ_LIMIT	   = 0x14,
    293	MLX4_EVENT_TYPE_CQ_ERROR	   = 0x04,
    294	MLX4_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
    295	MLX4_EVENT_TYPE_EEC_CATAS_ERROR	   = 0x06,
    296	MLX4_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
    297	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
    298	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
    299	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
    300	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
    301	MLX4_EVENT_TYPE_PORT_CHANGE	   = 0x09,
    302	MLX4_EVENT_TYPE_EQ_OVERFLOW	   = 0x0f,
    303	MLX4_EVENT_TYPE_ECC_DETECT	   = 0x0e,
    304	MLX4_EVENT_TYPE_CMD		   = 0x0a,
    305	MLX4_EVENT_TYPE_VEP_UPDATE	   = 0x19,
    306	MLX4_EVENT_TYPE_COMM_CHANNEL	   = 0x18,
    307	MLX4_EVENT_TYPE_OP_REQUIRED	   = 0x1a,
    308	MLX4_EVENT_TYPE_FATAL_WARNING	   = 0x1b,
    309	MLX4_EVENT_TYPE_FLR_EVENT	   = 0x1c,
    310	MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
    311	MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT  = 0x3e,
    312	MLX4_EVENT_TYPE_NONE		   = 0xff,
    313};
    314
    315enum {
    316	MLX4_PORT_CHANGE_SUBTYPE_DOWN	= 1,
    317	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE	= 4
    318};
    319
    320enum {
    321	MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE		= 1,
    322	MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE	= 2,
    323};
    324
    325enum {
    326	MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
    327};
    328
    329enum slave_port_state {
    330	SLAVE_PORT_DOWN = 0,
    331	SLAVE_PENDING_UP,
    332	SLAVE_PORT_UP,
    333};
    334
    335enum slave_port_gen_event {
    336	SLAVE_PORT_GEN_EVENT_DOWN = 0,
    337	SLAVE_PORT_GEN_EVENT_UP,
    338	SLAVE_PORT_GEN_EVENT_NONE,
    339};
    340
    341enum slave_port_state_event {
    342	MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
    343	MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
    344	MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
    345	MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
    346};
    347
    348enum {
    349	MLX4_PERM_LOCAL_READ	= 1 << 10,
    350	MLX4_PERM_LOCAL_WRITE	= 1 << 11,
    351	MLX4_PERM_REMOTE_READ	= 1 << 12,
    352	MLX4_PERM_REMOTE_WRITE	= 1 << 13,
    353	MLX4_PERM_ATOMIC	= 1 << 14,
    354	MLX4_PERM_BIND_MW	= 1 << 15,
    355	MLX4_PERM_MASK		= 0xFC00
    356};
    357
    358enum {
    359	MLX4_OPCODE_NOP			= 0x00,
    360	MLX4_OPCODE_SEND_INVAL		= 0x01,
    361	MLX4_OPCODE_RDMA_WRITE		= 0x08,
    362	MLX4_OPCODE_RDMA_WRITE_IMM	= 0x09,
    363	MLX4_OPCODE_SEND		= 0x0a,
    364	MLX4_OPCODE_SEND_IMM		= 0x0b,
    365	MLX4_OPCODE_LSO			= 0x0e,
    366	MLX4_OPCODE_RDMA_READ		= 0x10,
    367	MLX4_OPCODE_ATOMIC_CS		= 0x11,
    368	MLX4_OPCODE_ATOMIC_FA		= 0x12,
    369	MLX4_OPCODE_MASKED_ATOMIC_CS	= 0x14,
    370	MLX4_OPCODE_MASKED_ATOMIC_FA	= 0x15,
    371	MLX4_OPCODE_BIND_MW		= 0x18,
    372	MLX4_OPCODE_FMR			= 0x19,
    373	MLX4_OPCODE_LOCAL_INVAL		= 0x1b,
    374	MLX4_OPCODE_CONFIG_CMD		= 0x1f,
    375
    376	MLX4_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
    377	MLX4_RECV_OPCODE_SEND		= 0x01,
    378	MLX4_RECV_OPCODE_SEND_IMM	= 0x02,
    379	MLX4_RECV_OPCODE_SEND_INVAL	= 0x03,
    380
    381	MLX4_CQE_OPCODE_ERROR		= 0x1e,
    382	MLX4_CQE_OPCODE_RESIZE		= 0x16,
    383};
    384
    385enum {
    386	MLX4_STAT_RATE_OFFSET	= 5
    387};
    388
    389enum mlx4_protocol {
    390	MLX4_PROT_IB_IPV6 = 0,
    391	MLX4_PROT_ETH,
    392	MLX4_PROT_IB_IPV4,
    393	MLX4_PROT_FCOE
    394};
    395
    396enum {
    397	MLX4_MTT_FLAG_PRESENT		= 1
    398};
    399
    400enum mlx4_qp_region {
    401	MLX4_QP_REGION_FW = 0,
    402	MLX4_QP_REGION_RSS_RAW_ETH,
    403	MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
    404	MLX4_QP_REGION_ETH_ADDR,
    405	MLX4_QP_REGION_FC_ADDR,
    406	MLX4_QP_REGION_FC_EXCH,
    407	MLX4_NUM_QP_REGION
    408};
    409
    410enum mlx4_port_type {
    411	MLX4_PORT_TYPE_NONE	= 0,
    412	MLX4_PORT_TYPE_IB	= 1,
    413	MLX4_PORT_TYPE_ETH	= 2,
    414	MLX4_PORT_TYPE_AUTO	= 3
    415};
    416
    417enum mlx4_special_vlan_idx {
    418	MLX4_NO_VLAN_IDX        = 0,
    419	MLX4_VLAN_MISS_IDX,
    420	MLX4_VLAN_REGULAR
    421};
    422
    423enum mlx4_steer_type {
    424	MLX4_MC_STEER = 0,
    425	MLX4_UC_STEER,
    426	MLX4_NUM_STEERS
    427};
    428
    429enum mlx4_resource_usage {
    430	MLX4_RES_USAGE_NONE,
    431	MLX4_RES_USAGE_DRIVER,
    432	MLX4_RES_USAGE_USER_VERBS,
    433};
    434
    435enum {
    436	MLX4_NUM_FEXCH          = 64 * 1024,
    437};
    438
    439enum {
    440	MLX4_MAX_FAST_REG_PAGES = 511,
    441};
    442
    443enum {
    444	/*
    445	 * Max wqe size for rdma read is 512 bytes, so this
    446	 * limits our max_sge_rd as the wqe needs to fit:
    447	 * - ctrl segment (16 bytes)
    448	 * - rdma segment (16 bytes)
    449	 * - scatter elements (16 bytes each)
    450	 */
    451	MLX4_MAX_SGE_RD	= (512 - 16 - 16) / 16
    452};
    453
    454enum {
    455	MLX4_DEV_PMC_SUBTYPE_GUID_INFO	 = 0x14,
    456	MLX4_DEV_PMC_SUBTYPE_PORT_INFO	 = 0x15,
    457	MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE	 = 0x16,
    458	MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17,
    459};
    460
    461/* Port mgmt change event handling */
    462enum {
    463	MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK	= 1 << 0,
    464	MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK		= 1 << 1,
    465	MLX4_EQ_PORT_INFO_LID_CHANGE_MASK		= 1 << 2,
    466	MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK		= 1 << 3,
    467	MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK	= 1 << 4,
    468};
    469
    470union sl2vl_tbl_to_u64 {
    471	u8	sl8[8];
    472	u64	sl64;
    473};
    474
    475enum {
    476	MLX4_DEVICE_STATE_UP			= 1 << 0,
    477	MLX4_DEVICE_STATE_INTERNAL_ERROR	= 1 << 1,
    478};
    479
    480enum {
    481	MLX4_INTERFACE_STATE_UP		= 1 << 0,
    482	MLX4_INTERFACE_STATE_DELETION	= 1 << 1,
    483	MLX4_INTERFACE_STATE_NOWAIT	= 1 << 2,
    484};
    485
    486#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
    487			     MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
    488
    489enum mlx4_module_id {
    490	MLX4_MODULE_ID_SFP              = 0x3,
    491	MLX4_MODULE_ID_QSFP             = 0xC,
    492	MLX4_MODULE_ID_QSFP_PLUS        = 0xD,
    493	MLX4_MODULE_ID_QSFP28           = 0x11,
    494};
    495
    496enum { /* rl */
    497	MLX4_QP_RATE_LIMIT_NONE		= 0,
    498	MLX4_QP_RATE_LIMIT_KBS		= 1,
    499	MLX4_QP_RATE_LIMIT_MBS		= 2,
    500	MLX4_QP_RATE_LIMIT_GBS		= 3
    501};
    502
    503struct mlx4_rate_limit_caps {
    504	u16	num_rates; /* Number of different rates */
    505	u8	min_unit;
    506	u16	min_val;
    507	u8	max_unit;
    508	u16	max_val;
    509};
    510
    511static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
    512{
    513	return (major << 32) | (minor << 16) | subminor;
    514}
    515
    516struct mlx4_phys_caps {
    517	u32			gid_phys_table_len[MLX4_MAX_PORTS + 1];
    518	u32			pkey_phys_table_len[MLX4_MAX_PORTS + 1];
    519	u32			num_phys_eqs;
    520	u32			base_sqpn;
    521	u32			base_proxy_sqpn;
    522	u32			base_tunnel_sqpn;
    523};
    524
    525struct mlx4_spec_qps {
    526	u32 qp0_qkey;
    527	u32 qp0_proxy;
    528	u32 qp0_tunnel;
    529	u32 qp1_proxy;
    530	u32 qp1_tunnel;
    531};
    532
    533struct mlx4_caps {
    534	u64			fw_ver;
    535	u32			function;
    536	int			num_ports;
    537	int			vl_cap[MLX4_MAX_PORTS + 1];
    538	int			ib_mtu_cap[MLX4_MAX_PORTS + 1];
    539	__be32			ib_port_def_cap[MLX4_MAX_PORTS + 1];
    540	u64			def_mac[MLX4_MAX_PORTS + 1];
    541	int			eth_mtu_cap[MLX4_MAX_PORTS + 1];
    542	int			gid_table_len[MLX4_MAX_PORTS + 1];
    543	int			pkey_table_len[MLX4_MAX_PORTS + 1];
    544	int			trans_type[MLX4_MAX_PORTS + 1];
    545	int			vendor_oui[MLX4_MAX_PORTS + 1];
    546	int			wavelength[MLX4_MAX_PORTS + 1];
    547	u64			trans_code[MLX4_MAX_PORTS + 1];
    548	int			local_ca_ack_delay;
    549	int			num_uars;
    550	u32			uar_page_size;
    551	int			bf_reg_size;
    552	int			bf_regs_per_page;
    553	int			max_sq_sg;
    554	int			max_rq_sg;
    555	int			num_qps;
    556	int			max_wqes;
    557	int			max_sq_desc_sz;
    558	int			max_rq_desc_sz;
    559	int			max_qp_init_rdma;
    560	int			max_qp_dest_rdma;
    561	int			max_tc_eth;
    562	struct mlx4_spec_qps   *spec_qps;
    563	int			num_srqs;
    564	int			max_srq_wqes;
    565	int			max_srq_sge;
    566	int			reserved_srqs;
    567	int			num_cqs;
    568	int			max_cqes;
    569	int			reserved_cqs;
    570	int			num_sys_eqs;
    571	int			num_eqs;
    572	int			reserved_eqs;
    573	int			num_comp_vectors;
    574	int			num_mpts;
    575	int			num_mtts;
    576	int			fmr_reserved_mtts;
    577	int			reserved_mtts;
    578	int			reserved_mrws;
    579	int			reserved_uars;
    580	int			num_mgms;
    581	int			num_amgms;
    582	int			reserved_mcgs;
    583	int			num_qp_per_mgm;
    584	int			steering_mode;
    585	int			dmfs_high_steer_mode;
    586	int			fs_log_max_ucast_qp_range_size;
    587	int			num_pds;
    588	int			reserved_pds;
    589	int			max_xrcds;
    590	int			reserved_xrcds;
    591	int			mtt_entry_sz;
    592	u32			max_msg_sz;
    593	u32			page_size_cap;
    594	u64			flags;
    595	u64			flags2;
    596	u32			bmme_flags;
    597	u32			reserved_lkey;
    598	u16			stat_rate_support;
    599	u8			port_width_cap[MLX4_MAX_PORTS + 1];
    600	int			max_gso_sz;
    601	int			max_rss_tbl_sz;
    602	int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
    603	int			reserved_qps;
    604	int                     reserved_qps_base[MLX4_NUM_QP_REGION];
    605	int                     log_num_macs;
    606	int                     log_num_vlans;
    607	enum mlx4_port_type	port_type[MLX4_MAX_PORTS + 1];
    608	u8			supported_type[MLX4_MAX_PORTS + 1];
    609	u8                      suggested_type[MLX4_MAX_PORTS + 1];
    610	u8                      default_sense[MLX4_MAX_PORTS + 1];
    611	u32			port_mask[MLX4_MAX_PORTS + 1];
    612	enum mlx4_port_type	possible_type[MLX4_MAX_PORTS + 1];
    613	u32			max_counters;
    614	u8			port_ib_mtu[MLX4_MAX_PORTS + 1];
    615	u16			sqp_demux;
    616	u32			eqe_size;
    617	u32			cqe_size;
    618	u8			eqe_factor;
    619	u32			userspace_caps; /* userspace must be aware of these */
    620	u32			function_caps;  /* VFs must be aware of these */
    621	u16			hca_core_clock;
    622	u64			phys_port_id[MLX4_MAX_PORTS + 1];
    623	int			tunnel_offload_mode;
    624	u8			rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
    625	u8			phv_bit[MLX4_MAX_PORTS + 1];
    626	u8			alloc_res_qp_mask;
    627	u32			dmfs_high_rate_qpn_base;
    628	u32			dmfs_high_rate_qpn_range;
    629	u32			vf_caps;
    630	bool			wol_port[MLX4_MAX_PORTS + 1];
    631	struct mlx4_rate_limit_caps rl_caps;
    632	u32			health_buffer_addrs;
    633	bool			map_clock_to_user;
    634};
    635
    636struct mlx4_buf_list {
    637	void		       *buf;
    638	dma_addr_t		map;
    639};
    640
    641struct mlx4_buf {
    642	struct mlx4_buf_list	direct;
    643	struct mlx4_buf_list   *page_list;
    644	int			nbufs;
    645	int			npages;
    646	int			page_shift;
    647};
    648
    649struct mlx4_mtt {
    650	u32			offset;
    651	int			order;
    652	int			page_shift;
    653};
    654
    655enum {
    656	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
    657};
    658
    659struct mlx4_db_pgdir {
    660	struct list_head	list;
    661	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
    662	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
    663	unsigned long	       *bits[2];
    664	__be32		       *db_page;
    665	dma_addr_t		db_dma;
    666};
    667
    668struct mlx4_ib_user_db_page;
    669
    670struct mlx4_db {
    671	__be32			*db;
    672	union {
    673		struct mlx4_db_pgdir		*pgdir;
    674		struct mlx4_ib_user_db_page	*user_page;
    675	}			u;
    676	dma_addr_t		dma;
    677	int			index;
    678	int			order;
    679};
    680
    681struct mlx4_hwq_resources {
    682	struct mlx4_db		db;
    683	struct mlx4_mtt		mtt;
    684	struct mlx4_buf		buf;
    685};
    686
    687struct mlx4_mr {
    688	struct mlx4_mtt		mtt;
    689	u64			iova;
    690	u64			size;
    691	u32			key;
    692	u32			pd;
    693	u32			access;
    694	int			enabled;
    695};
    696
    697enum mlx4_mw_type {
    698	MLX4_MW_TYPE_1 = 1,
    699	MLX4_MW_TYPE_2 = 2,
    700};
    701
    702struct mlx4_mw {
    703	u32			key;
    704	u32			pd;
    705	enum mlx4_mw_type	type;
    706	int			enabled;
    707};
    708
    709struct mlx4_uar {
    710	unsigned long		pfn;
    711	int			index;
    712	struct list_head	bf_list;
    713	unsigned		free_bf_bmap;
    714	void __iomem	       *map;
    715	void __iomem	       *bf_map;
    716};
    717
    718struct mlx4_bf {
    719	unsigned int		offset;
    720	int			buf_size;
    721	struct mlx4_uar	       *uar;
    722	void __iomem	       *reg;
    723};
    724
    725struct mlx4_cq {
    726	void (*comp)		(struct mlx4_cq *);
    727	void (*event)		(struct mlx4_cq *, enum mlx4_event);
    728
    729	struct mlx4_uar	       *uar;
    730
    731	u32			cons_index;
    732
    733	u16                     irq;
    734	__be32		       *set_ci_db;
    735	__be32		       *arm_db;
    736	int			arm_sn;
    737
    738	int			cqn;
    739	unsigned		vector;
    740
    741	refcount_t		refcount;
    742	struct completion	free;
    743	struct {
    744		struct list_head list;
    745		void (*comp)(struct mlx4_cq *);
    746		void		*priv;
    747	} tasklet_ctx;
    748	int		reset_notify_added;
    749	struct list_head	reset_notify;
    750	u8			usage;
    751};
    752
    753struct mlx4_qp {
    754	void (*event)		(struct mlx4_qp *, enum mlx4_event);
    755
    756	int			qpn;
    757
    758	refcount_t		refcount;
    759	struct completion	free;
    760	u8			usage;
    761};
    762
    763struct mlx4_srq {
    764	void (*event)		(struct mlx4_srq *, enum mlx4_event);
    765
    766	int			srqn;
    767	int			max;
    768	int			max_gs;
    769	int			wqe_shift;
    770
    771	refcount_t		refcount;
    772	struct completion	free;
    773};
    774
    775struct mlx4_av {
    776	__be32			port_pd;
    777	u8			reserved1;
    778	u8			g_slid;
    779	__be16			dlid;
    780	u8			reserved2;
    781	u8			gid_index;
    782	u8			stat_rate;
    783	u8			hop_limit;
    784	__be32			sl_tclass_flowlabel;
    785	u8			dgid[16];
    786};
    787
    788struct mlx4_eth_av {
    789	__be32		port_pd;
    790	u8		reserved1;
    791	u8		smac_idx;
    792	u16		reserved2;
    793	u8		reserved3;
    794	u8		gid_index;
    795	u8		stat_rate;
    796	u8		hop_limit;
    797	__be32		sl_tclass_flowlabel;
    798	u8		dgid[16];
    799	u8		s_mac[6];
    800	u8		reserved4[2];
    801	__be16		vlan;
    802	u8		mac[ETH_ALEN];
    803};
    804
    805union mlx4_ext_av {
    806	struct mlx4_av		ib;
    807	struct mlx4_eth_av	eth;
    808};
    809
    810/* Counters should be saturate once they reach their maximum value */
    811#define ASSIGN_32BIT_COUNTER(counter, value) do {	\
    812	if ((value) > U32_MAX)				\
    813		counter = cpu_to_be32(U32_MAX);		\
    814	else						\
    815		counter = cpu_to_be32(value);		\
    816} while (0)
    817
    818struct mlx4_counter {
    819	u8	reserved1[3];
    820	u8	counter_mode;
    821	__be32	num_ifc;
    822	u32	reserved2[2];
    823	__be64	rx_frames;
    824	__be64	rx_bytes;
    825	__be64	tx_frames;
    826	__be64	tx_bytes;
    827};
    828
    829struct mlx4_quotas {
    830	int qp;
    831	int cq;
    832	int srq;
    833	int mpt;
    834	int mtt;
    835	int counter;
    836	int xrcd;
    837};
    838
    839struct mlx4_vf_dev {
    840	u8			min_port;
    841	u8			n_ports;
    842};
    843
    844struct mlx4_fw_crdump {
    845	bool snapshot_enable;
    846	struct devlink_region *region_crspace;
    847	struct devlink_region *region_fw_health;
    848};
    849
    850enum mlx4_pci_status {
    851	MLX4_PCI_STATUS_DISABLED,
    852	MLX4_PCI_STATUS_ENABLED,
    853};
    854
    855struct mlx4_dev_persistent {
    856	struct pci_dev	       *pdev;
    857	struct mlx4_dev	       *dev;
    858	int                     nvfs[MLX4_MAX_PORTS + 1];
    859	int			num_vfs;
    860	enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
    861	enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
    862	struct work_struct      catas_work;
    863	struct workqueue_struct *catas_wq;
    864	struct mutex	device_state_mutex; /* protect HW state */
    865	u8		state;
    866	struct mutex	interface_state_mutex; /* protect SW state */
    867	u8	interface_state;
    868	struct mutex		pci_status_mutex; /* sync pci state */
    869	enum mlx4_pci_status	pci_status;
    870	struct mlx4_fw_crdump	crdump;
    871};
    872
    873struct mlx4_dev {
    874	struct mlx4_dev_persistent *persist;
    875	unsigned long		flags;
    876	unsigned long		num_slaves;
    877	struct mlx4_caps	caps;
    878	struct mlx4_phys_caps	phys_caps;
    879	struct mlx4_quotas	quotas;
    880	struct radix_tree_root	qp_table_tree;
    881	u8			rev_id;
    882	u8			port_random_macs;
    883	char			board_id[MLX4_BOARD_ID_LEN];
    884	int			numa_node;
    885	int			oper_log_mgm_entry_size;
    886	u64			regid_promisc_array[MLX4_MAX_PORTS + 1];
    887	u64			regid_allmulti_array[MLX4_MAX_PORTS + 1];
    888	struct mlx4_vf_dev     *dev_vfs;
    889	u8  uar_page_shift;
    890};
    891
    892struct mlx4_clock_params {
    893	u64 offset;
    894	u8 bar;
    895	u8 size;
    896};
    897
    898struct mlx4_eqe {
    899	u8			reserved1;
    900	u8			type;
    901	u8			reserved2;
    902	u8			subtype;
    903	union {
    904		u32		raw[6];
    905		struct {
    906			__be32	cqn;
    907		} __packed comp;
    908		struct {
    909			u16	reserved1;
    910			__be16	token;
    911			u32	reserved2;
    912			u8	reserved3[3];
    913			u8	status;
    914			__be64	out_param;
    915		} __packed cmd;
    916		struct {
    917			__be32	qpn;
    918		} __packed qp;
    919		struct {
    920			__be32	srqn;
    921		} __packed srq;
    922		struct {
    923			__be32	cqn;
    924			u32	reserved1;
    925			u8	reserved2[3];
    926			u8	syndrome;
    927		} __packed cq_err;
    928		struct {
    929			u32	reserved1[2];
    930			__be32	port;
    931		} __packed port_change;
    932		struct {
    933			#define COMM_CHANNEL_BIT_ARRAY_SIZE	4
    934			u32 reserved;
    935			u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
    936		} __packed comm_channel_arm;
    937		struct {
    938			u8	port;
    939			u8	reserved[3];
    940			__be64	mac;
    941		} __packed mac_update;
    942		struct {
    943			__be32	slave_id;
    944		} __packed flr_event;
    945		struct {
    946			__be16  current_temperature;
    947			__be16  warning_threshold;
    948		} __packed warming;
    949		struct {
    950			u8 reserved[3];
    951			u8 port;
    952			union {
    953				struct {
    954					__be16 mstr_sm_lid;
    955					__be16 port_lid;
    956					__be32 changed_attr;
    957					u8 reserved[3];
    958					u8 mstr_sm_sl;
    959					__be64 gid_prefix;
    960				} __packed port_info;
    961				struct {
    962					__be32 block_ptr;
    963					__be32 tbl_entries_mask;
    964				} __packed tbl_change_info;
    965				struct {
    966					u8 sl2vl_table[8];
    967				} __packed sl2vl_tbl_change_info;
    968			} params;
    969		} __packed port_mgmt_change;
    970		struct {
    971			u8 reserved[3];
    972			u8 port;
    973			u32 reserved1[5];
    974		} __packed bad_cable;
    975	}			event;
    976	u8			slave_id;
    977	u8			reserved3[2];
    978	u8			owner;
    979} __packed;
    980
    981struct mlx4_init_port_param {
    982	int			set_guid0;
    983	int			set_node_guid;
    984	int			set_si_guid;
    985	u16			mtu;
    986	int			port_width_cap;
    987	u16			vl_cap;
    988	u16			max_gid;
    989	u16			max_pkey;
    990	u64			guid0;
    991	u64			node_guid;
    992	u64			si_guid;
    993};
    994
    995#define MAD_IFC_DATA_SZ 192
    996/* MAD IFC Mailbox */
    997struct mlx4_mad_ifc {
    998	u8	base_version;
    999	u8	mgmt_class;
   1000	u8	class_version;
   1001	u8	method;
   1002	__be16	status;
   1003	__be16	class_specific;
   1004	__be64	tid;
   1005	__be16	attr_id;
   1006	__be16	resv;
   1007	__be32	attr_mod;
   1008	__be64	mkey;
   1009	__be16	dr_slid;
   1010	__be16	dr_dlid;
   1011	u8	reserved[28];
   1012	u8	data[MAD_IFC_DATA_SZ];
   1013} __packed;
   1014
   1015#define mlx4_foreach_port(port, dev, type)				\
   1016	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	\
   1017		if ((type) == (dev)->caps.port_mask[(port)])
   1018
   1019#define mlx4_foreach_ib_transport_port(port, dev)                         \
   1020	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)       \
   1021		if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
   1022		    ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH))
   1023
   1024#define MLX4_INVALID_SLAVE_ID	0xFF
   1025#define MLX4_SINK_COUNTER_INDEX(dev)	(dev->caps.max_counters - 1)
   1026
   1027void handle_port_mgmt_change_event(struct work_struct *work);
   1028
   1029static inline int mlx4_master_func_num(struct mlx4_dev *dev)
   1030{
   1031	return dev->caps.function;
   1032}
   1033
   1034static inline int mlx4_is_master(struct mlx4_dev *dev)
   1035{
   1036	return dev->flags & MLX4_FLAG_MASTER;
   1037}
   1038
   1039static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
   1040{
   1041	return dev->phys_caps.base_sqpn + 8 +
   1042		16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
   1043}
   1044
   1045static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
   1046{
   1047	return (qpn < dev->phys_caps.base_sqpn + 8 +
   1048		16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
   1049		qpn >= dev->phys_caps.base_sqpn) ||
   1050	       (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
   1051}
   1052
   1053static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
   1054{
   1055	int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
   1056
   1057	if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
   1058		return 1;
   1059
   1060	return 0;
   1061}
   1062
   1063static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
   1064{
   1065	return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
   1066}
   1067
   1068static inline int mlx4_is_slave(struct mlx4_dev *dev)
   1069{
   1070	return dev->flags & MLX4_FLAG_SLAVE;
   1071}
   1072
   1073static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
   1074{
   1075	return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
   1076}
   1077
   1078int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
   1079		   struct mlx4_buf *buf);
   1080void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
   1081static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
   1082{
   1083	if (buf->nbufs == 1)
   1084		return buf->direct.buf + offset;
   1085	else
   1086		return buf->page_list[offset >> PAGE_SHIFT].buf +
   1087			(offset & (PAGE_SIZE - 1));
   1088}
   1089
   1090int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
   1091void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
   1092int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
   1093void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
   1094
   1095int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
   1096void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
   1097int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
   1098void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
   1099
   1100int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
   1101		  struct mlx4_mtt *mtt);
   1102void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
   1103u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
   1104
   1105int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
   1106		  int npages, int page_shift, struct mlx4_mr *mr);
   1107int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
   1108int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
   1109int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
   1110		  struct mlx4_mw *mw);
   1111void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
   1112int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
   1113int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
   1114		   int start_index, int npages, u64 *page_list);
   1115int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
   1116		       struct mlx4_buf *buf);
   1117
   1118int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
   1119void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
   1120
   1121int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
   1122		       int size);
   1123void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
   1124		       int size);
   1125
   1126int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
   1127		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
   1128		  unsigned int vector, int collapsed, int timestamp_en,
   1129		  void *buf_addr, bool user_cq);
   1130void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
   1131int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
   1132			  int *base, u8 flags, u8 usage);
   1133void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
   1134
   1135int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
   1136void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
   1137
   1138int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
   1139		   struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
   1140void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
   1141int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
   1142int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
   1143
   1144int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
   1145int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
   1146
   1147int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
   1148			int block_mcast_loopback, enum mlx4_protocol prot);
   1149int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
   1150			enum mlx4_protocol prot);
   1151int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
   1152			  u8 port, int block_mcast_loopback,
   1153			  enum mlx4_protocol protocol, u64 *reg_id);
   1154int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
   1155			  enum mlx4_protocol protocol, u64 reg_id);
   1156
   1157enum {
   1158	MLX4_DOMAIN_UVERBS	= 0x1000,
   1159	MLX4_DOMAIN_ETHTOOL     = 0x2000,
   1160	MLX4_DOMAIN_RFS         = 0x3000,
   1161	MLX4_DOMAIN_NIC    = 0x5000,
   1162};
   1163
   1164enum mlx4_net_trans_rule_id {
   1165	MLX4_NET_TRANS_RULE_ID_ETH = 0,
   1166	MLX4_NET_TRANS_RULE_ID_IB,
   1167	MLX4_NET_TRANS_RULE_ID_IPV6,
   1168	MLX4_NET_TRANS_RULE_ID_IPV4,
   1169	MLX4_NET_TRANS_RULE_ID_TCP,
   1170	MLX4_NET_TRANS_RULE_ID_UDP,
   1171	MLX4_NET_TRANS_RULE_ID_VXLAN,
   1172	MLX4_NET_TRANS_RULE_NUM, /* should be last */
   1173};
   1174
   1175extern const u16 __sw_id_hw[];
   1176
   1177static inline int map_hw_to_sw_id(u16 header_id)
   1178{
   1179
   1180	int i;
   1181	for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
   1182		if (header_id == __sw_id_hw[i])
   1183			return i;
   1184	}
   1185	return -EINVAL;
   1186}
   1187
   1188enum mlx4_net_trans_promisc_mode {
   1189	MLX4_FS_REGULAR = 1,
   1190	MLX4_FS_ALL_DEFAULT,
   1191	MLX4_FS_MC_DEFAULT,
   1192	MLX4_FS_MIRROR_RX_PORT,
   1193	MLX4_FS_MIRROR_SX_PORT,
   1194	MLX4_FS_UC_SNIFFER,
   1195	MLX4_FS_MC_SNIFFER,
   1196	MLX4_FS_MODE_NUM, /* should be last */
   1197};
   1198
   1199struct mlx4_spec_eth {
   1200	u8	dst_mac[ETH_ALEN];
   1201	u8	dst_mac_msk[ETH_ALEN];
   1202	u8	src_mac[ETH_ALEN];
   1203	u8	src_mac_msk[ETH_ALEN];
   1204	u8	ether_type_enable;
   1205	__be16	ether_type;
   1206	__be16	vlan_id_msk;
   1207	__be16	vlan_id;
   1208};
   1209
   1210struct mlx4_spec_tcp_udp {
   1211	__be16 dst_port;
   1212	__be16 dst_port_msk;
   1213	__be16 src_port;
   1214	__be16 src_port_msk;
   1215};
   1216
   1217struct mlx4_spec_ipv4 {
   1218	__be32 dst_ip;
   1219	__be32 dst_ip_msk;
   1220	__be32 src_ip;
   1221	__be32 src_ip_msk;
   1222};
   1223
   1224struct mlx4_spec_ib {
   1225	__be32  l3_qpn;
   1226	__be32	qpn_msk;
   1227	u8	dst_gid[16];
   1228	u8	dst_gid_msk[16];
   1229};
   1230
   1231struct mlx4_spec_vxlan {
   1232	__be32 vni;
   1233	__be32 vni_mask;
   1234
   1235};
   1236
   1237struct mlx4_spec_list {
   1238	struct	list_head list;
   1239	enum	mlx4_net_trans_rule_id id;
   1240	union {
   1241		struct mlx4_spec_eth eth;
   1242		struct mlx4_spec_ib ib;
   1243		struct mlx4_spec_ipv4 ipv4;
   1244		struct mlx4_spec_tcp_udp tcp_udp;
   1245		struct mlx4_spec_vxlan vxlan;
   1246	};
   1247};
   1248
   1249enum mlx4_net_trans_hw_rule_queue {
   1250	MLX4_NET_TRANS_Q_FIFO,
   1251	MLX4_NET_TRANS_Q_LIFO,
   1252};
   1253
   1254struct mlx4_net_trans_rule {
   1255	struct	list_head list;
   1256	enum	mlx4_net_trans_hw_rule_queue queue_mode;
   1257	bool	exclusive;
   1258	bool	allow_loopback;
   1259	enum	mlx4_net_trans_promisc_mode promisc_mode;
   1260	u8	port;
   1261	u16	priority;
   1262	u32	qpn;
   1263};
   1264
   1265struct mlx4_net_trans_rule_hw_ctrl {
   1266	__be16 prio;
   1267	u8 type;
   1268	u8 flags;
   1269	u8 rsvd1;
   1270	u8 funcid;
   1271	u8 vep;
   1272	u8 port;
   1273	__be32 qpn;
   1274	__be32 rsvd2;
   1275};
   1276
   1277struct mlx4_net_trans_rule_hw_ib {
   1278	u8 size;
   1279	u8 rsvd1;
   1280	__be16 id;
   1281	u32 rsvd2;
   1282	__be32 l3_qpn;
   1283	__be32 qpn_mask;
   1284	u8 dst_gid[16];
   1285	u8 dst_gid_msk[16];
   1286} __packed;
   1287
   1288struct mlx4_net_trans_rule_hw_eth {
   1289	u8	size;
   1290	u8	rsvd;
   1291	__be16	id;
   1292	u8	rsvd1[6];
   1293	u8	dst_mac[6];
   1294	u16	rsvd2;
   1295	u8	dst_mac_msk[6];
   1296	u16	rsvd3;
   1297	u8	src_mac[6];
   1298	u16	rsvd4;
   1299	u8	src_mac_msk[6];
   1300	u8      rsvd5;
   1301	u8      ether_type_enable;
   1302	__be16  ether_type;
   1303	__be16  vlan_tag_msk;
   1304	__be16  vlan_tag;
   1305} __packed;
   1306
   1307struct mlx4_net_trans_rule_hw_tcp_udp {
   1308	u8	size;
   1309	u8	rsvd;
   1310	__be16	id;
   1311	__be16	rsvd1[3];
   1312	__be16	dst_port;
   1313	__be16	rsvd2;
   1314	__be16	dst_port_msk;
   1315	__be16	rsvd3;
   1316	__be16	src_port;
   1317	__be16	rsvd4;
   1318	__be16	src_port_msk;
   1319} __packed;
   1320
   1321struct mlx4_net_trans_rule_hw_ipv4 {
   1322	u8	size;
   1323	u8	rsvd;
   1324	__be16	id;
   1325	__be32	rsvd1;
   1326	__be32	dst_ip;
   1327	__be32	dst_ip_msk;
   1328	__be32	src_ip;
   1329	__be32	src_ip_msk;
   1330} __packed;
   1331
   1332struct mlx4_net_trans_rule_hw_vxlan {
   1333	u8	size;
   1334	u8	rsvd;
   1335	__be16	id;
   1336	__be32	rsvd1;
   1337	__be32	vni;
   1338	__be32	vni_mask;
   1339} __packed;
   1340
   1341struct _rule_hw {
   1342	union {
   1343		struct {
   1344			u8 size;
   1345			u8 rsvd;
   1346			__be16 id;
   1347		};
   1348		struct mlx4_net_trans_rule_hw_eth eth;
   1349		struct mlx4_net_trans_rule_hw_ib ib;
   1350		struct mlx4_net_trans_rule_hw_ipv4 ipv4;
   1351		struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
   1352		struct mlx4_net_trans_rule_hw_vxlan vxlan;
   1353	};
   1354};
   1355
   1356enum {
   1357	VXLAN_STEER_BY_OUTER_MAC	= 1 << 0,
   1358	VXLAN_STEER_BY_OUTER_VLAN	= 1 << 1,
   1359	VXLAN_STEER_BY_VSID_VNI		= 1 << 2,
   1360	VXLAN_STEER_BY_INNER_MAC	= 1 << 3,
   1361	VXLAN_STEER_BY_INNER_VLAN	= 1 << 4,
   1362};
   1363
   1364enum {
   1365	MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2,
   1366};
   1367
   1368int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
   1369				enum mlx4_net_trans_promisc_mode mode);
   1370int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
   1371				   enum mlx4_net_trans_promisc_mode mode);
   1372int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
   1373int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
   1374int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
   1375int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
   1376int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
   1377
   1378int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
   1379void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
   1380int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
   1381int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
   1382int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
   1383			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
   1384int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac);
   1385int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu);
   1386int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
   1387			   u8 promisc);
   1388int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
   1389int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
   1390			    u8 ignore_fcs_value);
   1391int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
   1392int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
   1393int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
   1394int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port,
   1395				      bool *vlan_offload_disabled);
   1396void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
   1397				       struct _rule_hw *eth_header);
   1398int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
   1399int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
   1400int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
   1401void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
   1402
   1403int mlx4_SYNC_TPT(struct mlx4_dev *dev);
   1404int mlx4_test_interrupt(struct mlx4_dev *dev, int vector);
   1405int mlx4_test_async(struct mlx4_dev *dev);
   1406int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier,
   1407			     const u32 offset[], u32 value[],
   1408			     size_t array_len, u8 port);
   1409u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
   1410bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
   1411struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
   1412int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
   1413void mlx4_release_eq(struct mlx4_dev *dev, int vec);
   1414
   1415int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
   1416int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
   1417
   1418int mlx4_get_phys_port_id(struct mlx4_dev *dev);
   1419int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
   1420int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
   1421
   1422int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage);
   1423void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
   1424int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
   1425
   1426void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
   1427			 int port);
   1428__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
   1429void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
   1430int mlx4_flow_attach(struct mlx4_dev *dev,
   1431		     struct mlx4_net_trans_rule *rule, u64 *reg_id);
   1432int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
   1433int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
   1434				    enum mlx4_net_trans_promisc_mode flow_type);
   1435int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
   1436				  enum mlx4_net_trans_rule_id id);
   1437int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
   1438
   1439int mlx4_tunnel_steer_add(struct mlx4_dev *dev, const unsigned char *addr,
   1440			  int port, int qpn, u16 prio, u64 *reg_id);
   1441
   1442void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
   1443			  int i, int val);
   1444
   1445int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
   1446
   1447int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
   1448int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
   1449int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
   1450int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
   1451int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
   1452enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
   1453int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
   1454
   1455void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
   1456__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
   1457
   1458int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
   1459				 int *slave_id);
   1460int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
   1461				 u8 *gid);
   1462
   1463int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
   1464				      u32 max_range_qpn);
   1465
   1466u64 mlx4_read_clock(struct mlx4_dev *dev);
   1467
   1468struct mlx4_active_ports {
   1469	DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
   1470};
   1471/* Returns a bitmap of the physical ports which are assigned to slave */
   1472struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
   1473
   1474/* Returns the physical port that represents the virtual port of the slave, */
   1475/* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
   1476/* mapping is returned.							    */
   1477int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
   1478
   1479struct mlx4_slaves_pport {
   1480	DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
   1481};
   1482/* Returns a bitmap of all slaves that are assigned to port. */
   1483struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
   1484						   int port);
   1485
   1486/* Returns a bitmap of all slaves that are assigned exactly to all the */
   1487/* the ports that are set in crit_ports.			       */
   1488struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
   1489		struct mlx4_dev *dev,
   1490		const struct mlx4_active_ports *crit_ports);
   1491
   1492/* Returns the slave's virtual port that represents the physical port. */
   1493int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
   1494
   1495int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
   1496
   1497int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
   1498int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
   1499int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port);
   1500int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
   1501int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
   1502int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
   1503int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
   1504				 int enable);
   1505
   1506struct mlx4_mpt_entry;
   1507int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
   1508		       struct mlx4_mpt_entry ***mpt_entry);
   1509int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
   1510			 struct mlx4_mpt_entry **mpt_entry);
   1511int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
   1512			 u32 pdn);
   1513int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
   1514			     struct mlx4_mpt_entry *mpt_entry,
   1515			     u32 access);
   1516void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
   1517			struct mlx4_mpt_entry **mpt_entry);
   1518void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
   1519int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
   1520			    u64 iova, u64 size, int npages,
   1521			    int page_shift, struct mlx4_mpt_entry *mpt_entry);
   1522
   1523int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
   1524			 u16 offset, u16 size, u8 *data);
   1525int mlx4_max_tc(struct mlx4_dev *dev);
   1526
   1527/* Returns true if running in low memory profile (kdump kernel) */
   1528static inline bool mlx4_low_memory_profile(void)
   1529{
   1530	return is_kdump_kernel();
   1531}
   1532
   1533/* ACCESS REG commands */
   1534enum mlx4_access_reg_method {
   1535	MLX4_ACCESS_REG_QUERY = 0x1,
   1536	MLX4_ACCESS_REG_WRITE = 0x2,
   1537};
   1538
   1539/* ACCESS PTYS Reg command */
   1540enum mlx4_ptys_proto {
   1541	MLX4_PTYS_IB = 1<<0,
   1542	MLX4_PTYS_EN = 1<<2,
   1543};
   1544
   1545enum mlx4_ptys_flags {
   1546	MLX4_PTYS_AN_DISABLE_CAP   = 1 << 5,
   1547	MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6,
   1548};
   1549
   1550struct mlx4_ptys_reg {
   1551	u8 flags;
   1552	u8 local_port;
   1553	u8 resrvd2;
   1554	u8 proto_mask;
   1555	__be32 resrvd3[2];
   1556	__be32 eth_proto_cap;
   1557	__be16 ib_width_cap;
   1558	__be16 ib_speed_cap;
   1559	__be32 resrvd4;
   1560	__be32 eth_proto_admin;
   1561	__be16 ib_width_admin;
   1562	__be16 ib_speed_admin;
   1563	__be32 resrvd5;
   1564	__be32 eth_proto_oper;
   1565	__be16 ib_width_oper;
   1566	__be16 ib_speed_oper;
   1567	__be32 resrvd6;
   1568	__be32 eth_proto_lp_adv;
   1569} __packed;
   1570
   1571int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
   1572			 enum mlx4_access_reg_method method,
   1573			 struct mlx4_ptys_reg *ptys_reg);
   1574
   1575int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
   1576				   struct mlx4_clock_params *params);
   1577
   1578static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index)
   1579{
   1580	return (index << (PAGE_SHIFT - dev->uar_page_shift));
   1581}
   1582
   1583static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev)
   1584{
   1585	/* The first 128 UARs are used for EQ doorbells */
   1586	return (128 >> (PAGE_SHIFT - dev->uar_page_shift));
   1587}
   1588#endif /* MLX4_DEVICE_H */