cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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doorbell.h (2271B)

      1/*
      2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
      3 *
      4 * This software is available to you under a choice of one of two
      5 * licenses.  You may choose to be licensed under the terms of the GNU
      6 * General Public License (GPL) Version 2, available from the file
      7 * COPYING in the main directory of this source tree, or the
      8 * OpenIB.org BSD license below:
      9 *
     10 *     Redistribution and use in source and binary forms, with or
     11 *     without modification, are permitted provided that the following
     12 *     conditions are met:
     13 *
     14 *      - Redistributions of source code must retain the above
     15 *        copyright notice, this list of conditions and the following
     16 *        disclaimer.
     17 *
     18 *      - Redistributions in binary form must reproduce the above
     19 *        copyright notice, this list of conditions and the following
     20 *        disclaimer in the documentation and/or other materials
     21 *        provided with the distribution.
     22 *
     23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
     27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
     28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
     29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     30 * SOFTWARE.
     31 */
     32
     33#ifndef MLX5_DOORBELL_H
     34#define MLX5_DOORBELL_H
     35
     36#define MLX5_BF_OFFSET	      0x800
     37#define MLX5_CQ_DOORBELL      0x20
     38
     39/* Assume that we can just write a 64-bit doorbell atomically.  s390
     40 * actually doesn't have writeq() but S/390 systems don't even have
     41 * PCI so we won't worry about it.
     42 *
     43 * Note that the write is not atomic on 32-bit systems! In contrast to 64-bit
     44 * ones, it requires proper locking. mlx5_write64 doesn't do any locking, so use
     45 * it at your own discretion, protected by some kind of lock on 32 bits.
     46 *
     47 * TODO: use write{q,l}_relaxed()
     48 */
     49
     50static inline void mlx5_write64(__be32 val[2], void __iomem *dest)
     51{
     52#if BITS_PER_LONG == 64
     53	__raw_writeq(*(u64 *)val, dest);
     54#else
     55	__raw_writel((__force u32) val[0], dest);
     56	__raw_writel((__force u32) val[1], dest + 4);
     57#endif
     58}
     59
     60#endif /* MLX5_DOORBELL_H */