mlx5_ifc_fpga.h (9540B)
1/* 2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#ifndef MLX5_IFC_FPGA_H 33#define MLX5_IFC_FPGA_H 34 35struct mlx5_ifc_ipv4_layout_bits { 36 u8 reserved_at_0[0x60]; 37 38 u8 ipv4[0x20]; 39}; 40 41struct mlx5_ifc_ipv6_layout_bits { 42 u8 ipv6[16][0x8]; 43}; 44 45union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 46 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 47 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 48 u8 reserved_at_0[0x80]; 49}; 50 51enum { 52 MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9, 53}; 54 55enum { 56 MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2, 57}; 58 59struct mlx5_ifc_fpga_shell_caps_bits { 60 u8 max_num_qps[0x10]; 61 u8 reserved_at_10[0x8]; 62 u8 total_rcv_credits[0x8]; 63 64 u8 reserved_at_20[0xe]; 65 u8 qp_type[0x2]; 66 u8 reserved_at_30[0x5]; 67 u8 rae[0x1]; 68 u8 rwe[0x1]; 69 u8 rre[0x1]; 70 u8 reserved_at_38[0x4]; 71 u8 dc[0x1]; 72 u8 ud[0x1]; 73 u8 uc[0x1]; 74 u8 rc[0x1]; 75 76 u8 reserved_at_40[0x1a]; 77 u8 log_ddr_size[0x6]; 78 79 u8 max_fpga_qp_msg_size[0x20]; 80 81 u8 reserved_at_80[0x180]; 82}; 83 84struct mlx5_ifc_fpga_cap_bits { 85 u8 fpga_id[0x8]; 86 u8 fpga_device[0x18]; 87 88 u8 register_file_ver[0x20]; 89 90 u8 fpga_ctrl_modify[0x1]; 91 u8 reserved_at_41[0x5]; 92 u8 access_reg_query_mode[0x2]; 93 u8 reserved_at_48[0x6]; 94 u8 access_reg_modify_mode[0x2]; 95 u8 reserved_at_50[0x10]; 96 97 u8 reserved_at_60[0x20]; 98 99 u8 image_version[0x20]; 100 101 u8 image_date[0x20]; 102 103 u8 image_time[0x20]; 104 105 u8 shell_version[0x20]; 106 107 u8 reserved_at_100[0x80]; 108 109 struct mlx5_ifc_fpga_shell_caps_bits shell_caps; 110 111 u8 reserved_at_380[0x8]; 112 u8 ieee_vendor_id[0x18]; 113 114 u8 sandbox_product_version[0x10]; 115 u8 sandbox_product_id[0x10]; 116 117 u8 sandbox_basic_caps[0x20]; 118 119 u8 reserved_at_3e0[0x10]; 120 u8 sandbox_extended_caps_len[0x10]; 121 122 u8 sandbox_extended_caps_addr[0x40]; 123 124 u8 fpga_ddr_start_addr[0x40]; 125 126 u8 fpga_cr_space_start_addr[0x40]; 127 128 u8 fpga_ddr_size[0x20]; 129 130 u8 fpga_cr_space_size[0x20]; 131 132 u8 reserved_at_500[0x300]; 133}; 134 135enum { 136 MLX5_FPGA_CTRL_OPERATION_LOAD = 0x1, 137 MLX5_FPGA_CTRL_OPERATION_RESET = 0x2, 138 MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT = 0x3, 139 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON = 0x4, 140 MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF = 0x5, 141 MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX = 0x6, 142}; 143 144struct mlx5_ifc_fpga_ctrl_bits { 145 u8 reserved_at_0[0x8]; 146 u8 operation[0x8]; 147 u8 reserved_at_10[0x8]; 148 u8 status[0x8]; 149 150 u8 reserved_at_20[0x8]; 151 u8 flash_select_admin[0x8]; 152 u8 reserved_at_30[0x8]; 153 u8 flash_select_oper[0x8]; 154 155 u8 reserved_at_40[0x40]; 156}; 157 158enum { 159 MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1, 160 MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2, 161 MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3, 162 MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4, 163 MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5, 164 MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6, 165 MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7, 166}; 167 168struct mlx5_ifc_fpga_error_event_bits { 169 u8 reserved_at_0[0x40]; 170 171 u8 reserved_at_40[0x18]; 172 u8 syndrome[0x8]; 173 174 u8 reserved_at_60[0x80]; 175}; 176 177#define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64 178 179struct mlx5_ifc_fpga_access_reg_bits { 180 u8 reserved_at_0[0x20]; 181 182 u8 reserved_at_20[0x10]; 183 u8 size[0x10]; 184 185 u8 address[0x40]; 186 187 u8 data[0][0x8]; 188}; 189 190enum mlx5_ifc_fpga_qp_state { 191 MLX5_FPGA_QPC_STATE_INIT = 0x0, 192 MLX5_FPGA_QPC_STATE_ACTIVE = 0x1, 193 MLX5_FPGA_QPC_STATE_ERROR = 0x2, 194}; 195 196enum mlx5_ifc_fpga_qp_type { 197 MLX5_FPGA_QPC_QP_TYPE_SHELL_QP = 0x0, 198 MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP = 0x1, 199}; 200 201enum mlx5_ifc_fpga_qp_service_type { 202 MLX5_FPGA_QPC_ST_RC = 0x0, 203}; 204 205struct mlx5_ifc_fpga_qpc_bits { 206 u8 state[0x4]; 207 u8 reserved_at_4[0x1b]; 208 u8 qp_type[0x1]; 209 210 u8 reserved_at_20[0x4]; 211 u8 st[0x4]; 212 u8 reserved_at_28[0x10]; 213 u8 traffic_class[0x8]; 214 215 u8 ether_type[0x10]; 216 u8 prio[0x3]; 217 u8 dei[0x1]; 218 u8 vid[0xc]; 219 220 u8 reserved_at_60[0x20]; 221 222 u8 reserved_at_80[0x8]; 223 u8 next_rcv_psn[0x18]; 224 225 u8 reserved_at_a0[0x8]; 226 u8 next_send_psn[0x18]; 227 228 u8 reserved_at_c0[0x10]; 229 u8 pkey[0x10]; 230 231 u8 reserved_at_e0[0x8]; 232 u8 remote_qpn[0x18]; 233 234 u8 reserved_at_100[0x15]; 235 u8 rnr_retry[0x3]; 236 u8 reserved_at_118[0x5]; 237 u8 retry_count[0x3]; 238 239 u8 reserved_at_120[0x20]; 240 241 u8 reserved_at_140[0x10]; 242 u8 remote_mac_47_32[0x10]; 243 244 u8 remote_mac_31_0[0x20]; 245 246 u8 remote_ip[16][0x8]; 247 248 u8 reserved_at_200[0x40]; 249 250 u8 reserved_at_240[0x10]; 251 u8 fpga_mac_47_32[0x10]; 252 253 u8 fpga_mac_31_0[0x20]; 254 255 u8 fpga_ip[16][0x8]; 256}; 257 258struct mlx5_ifc_fpga_create_qp_in_bits { 259 u8 opcode[0x10]; 260 u8 reserved_at_10[0x10]; 261 262 u8 reserved_at_20[0x10]; 263 u8 op_mod[0x10]; 264 265 u8 reserved_at_40[0x40]; 266 267 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 268}; 269 270struct mlx5_ifc_fpga_create_qp_out_bits { 271 u8 status[0x8]; 272 u8 reserved_at_8[0x18]; 273 274 u8 syndrome[0x20]; 275 276 u8 reserved_at_40[0x8]; 277 u8 fpga_qpn[0x18]; 278 279 u8 reserved_at_60[0x20]; 280 281 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 282}; 283 284struct mlx5_ifc_fpga_modify_qp_in_bits { 285 u8 opcode[0x10]; 286 u8 reserved_at_10[0x10]; 287 288 u8 reserved_at_20[0x10]; 289 u8 op_mod[0x10]; 290 291 u8 reserved_at_40[0x8]; 292 u8 fpga_qpn[0x18]; 293 294 u8 field_select[0x20]; 295 296 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 297}; 298 299struct mlx5_ifc_fpga_modify_qp_out_bits { 300 u8 status[0x8]; 301 u8 reserved_at_8[0x18]; 302 303 u8 syndrome[0x20]; 304 305 u8 reserved_at_40[0x40]; 306}; 307 308struct mlx5_ifc_fpga_query_qp_in_bits { 309 u8 opcode[0x10]; 310 u8 reserved_at_10[0x10]; 311 312 u8 reserved_at_20[0x10]; 313 u8 op_mod[0x10]; 314 315 u8 reserved_at_40[0x8]; 316 u8 fpga_qpn[0x18]; 317 318 u8 reserved_at_60[0x20]; 319}; 320 321struct mlx5_ifc_fpga_query_qp_out_bits { 322 u8 status[0x8]; 323 u8 reserved_at_8[0x18]; 324 325 u8 syndrome[0x20]; 326 327 u8 reserved_at_40[0x40]; 328 329 struct mlx5_ifc_fpga_qpc_bits fpga_qpc; 330}; 331 332struct mlx5_ifc_fpga_query_qp_counters_in_bits { 333 u8 opcode[0x10]; 334 u8 reserved_at_10[0x10]; 335 336 u8 reserved_at_20[0x10]; 337 u8 op_mod[0x10]; 338 339 u8 clear[0x1]; 340 u8 reserved_at_41[0x7]; 341 u8 fpga_qpn[0x18]; 342 343 u8 reserved_at_60[0x20]; 344}; 345 346struct mlx5_ifc_fpga_query_qp_counters_out_bits { 347 u8 status[0x8]; 348 u8 reserved_at_8[0x18]; 349 350 u8 syndrome[0x20]; 351 352 u8 reserved_at_40[0x40]; 353 354 u8 rx_ack_packets[0x40]; 355 356 u8 rx_send_packets[0x40]; 357 358 u8 tx_ack_packets[0x40]; 359 360 u8 tx_send_packets[0x40]; 361 362 u8 rx_total_drop[0x40]; 363 364 u8 reserved_at_1c0[0x1c0]; 365}; 366 367struct mlx5_ifc_fpga_destroy_qp_in_bits { 368 u8 opcode[0x10]; 369 u8 reserved_at_10[0x10]; 370 371 u8 reserved_at_20[0x10]; 372 u8 op_mod[0x10]; 373 374 u8 reserved_at_40[0x8]; 375 u8 fpga_qpn[0x18]; 376 377 u8 reserved_at_60[0x20]; 378}; 379 380struct mlx5_ifc_fpga_destroy_qp_out_bits { 381 u8 status[0x8]; 382 u8 reserved_at_8[0x18]; 383 384 u8 syndrome[0x20]; 385 386 u8 reserved_at_40[0x40]; 387}; 388 389enum { 390 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED = 0x1, 391 MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED = 0x2, 392}; 393 394struct mlx5_ifc_fpga_qp_error_event_bits { 395 u8 reserved_at_0[0x40]; 396 397 u8 reserved_at_40[0x18]; 398 u8 syndrome[0x8]; 399 400 u8 reserved_at_60[0x60]; 401 402 u8 reserved_at_c0[0x8]; 403 u8 fpga_qpn[0x18]; 404}; 405#endif /* MLX5_IFC_FPGA_H */