cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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phy-dp.h (1842B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 2019 Cadence Design Systems Inc.
      4 */
      5
      6#ifndef __PHY_DP_H_
      7#define __PHY_DP_H_
      8
      9#include <linux/types.h>
     10
     11/**
     12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
     13 *
     14 * This structure is used to represent the configuration state of a
     15 * DisplayPort phy.
     16 */
     17struct phy_configure_opts_dp {
     18	/**
     19	 * @link_rate:
     20	 *
     21	 * Link Rate, in Mb/s, of the main link.
     22	 *
     23	 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
     24	 */
     25	unsigned int link_rate;
     26
     27	/**
     28	 * @lanes:
     29	 *
     30	 * Number of active, consecutive, data lanes, starting from
     31	 * lane 0, used for the transmissions on main link.
     32	 *
     33	 * Allowed values: 1, 2, 4
     34	 */
     35	unsigned int lanes;
     36
     37	/**
     38	 * @voltage:
     39	 *
     40	 * Voltage swing levels, as specified by DisplayPort specification,
     41	 * to be used by particular lanes. One value per lane.
     42	 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
     43	 *
     44	 * Maximum value: 3
     45	 */
     46	unsigned int voltage[4];
     47
     48	/**
     49	 * @pre:
     50	 *
     51	 * Pre-emphasis levels, as specified by DisplayPort specification, to be
     52	 * used by particular lanes. One value per lane.
     53	 *
     54	 * Maximum value: 3
     55	 */
     56	unsigned int pre[4];
     57
     58	/**
     59	 * @ssc:
     60	 *
     61	 * Flag indicating, whether or not to enable spread-spectrum clocking.
     62	 *
     63	 */
     64	u8 ssc : 1;
     65
     66	/**
     67	 * @set_rate:
     68	 *
     69	 * Flag indicating, whether or not reconfigure link rate and SSC to
     70	 * requested values.
     71	 *
     72	 */
     73	u8 set_rate : 1;
     74
     75	/**
     76	 * @set_lanes:
     77	 *
     78	 * Flag indicating, whether or not reconfigure lane count to
     79	 * requested value.
     80	 *
     81	 */
     82	u8 set_lanes : 1;
     83
     84	/**
     85	 * @set_voltages:
     86	 *
     87	 * Flag indicating, whether or not reconfigure voltage swing
     88	 * and pre-emphasis to requested values. Only lanes specified
     89	 * by "lanes" parameter will be affected.
     90	 *
     91	 */
     92	u8 set_voltages : 1;
     93};
     94
     95#endif /* __PHY_DP_H_ */