cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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davinci_asp.h (3351B)

      1/*
      2 * TI DaVinci Audio Serial Port support
      3 *
      4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
      5 *
      6 * This program is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU General Public License as
      8 * published by the Free Software Foundation version 2.
      9 *
     10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
     11 * kind, whether express or implied; without even the implied warranty
     12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
     13 * GNU General Public License for more details.
     14 */
     15
     16#ifndef __DAVINCI_ASP_H
     17#define __DAVINCI_ASP_H
     18
     19#include <linux/genalloc.h>
     20
     21struct davinci_mcasp_pdata {
     22	u32 tx_dma_offset;
     23	u32 rx_dma_offset;
     24	int asp_chan_q;	/* event queue number for ASP channel */
     25	int ram_chan_q;	/* event queue number for RAM channel */
     26	/*
     27	 * Allowing this is more efficient and eliminates left and right swaps
     28	 * caused by underruns, but will swap the left and right channels
     29	 * when compared to previous behavior.
     30	 */
     31	unsigned enable_channel_combine:1;
     32	unsigned sram_size_playback;
     33	unsigned sram_size_capture;
     34	struct gen_pool *sram_pool;
     35
     36	/*
     37	 * If McBSP peripheral gets the clock from an external pin,
     38	 * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
     39	 * and MCBSP_CLKS.
     40	 * Depending on different hardware connections it is possible
     41	 * to use this setting to change the behaviour of McBSP
     42	 * driver.
     43	 */
     44	int clk_input_pin;
     45
     46	/*
     47	 * This flag works when both clock and FS are outputs for the cpu
     48	 * and makes clock more accurate (FS is not symmetrical and the
     49	 * clock is very fast.
     50	 * The clock becoming faster is named
     51	 * i2s continuous serial clock (I2S_SCK) and it is an externally
     52	 * visible bit clock.
     53	 *
     54	 * first line : WordSelect
     55	 * second line : ContinuousSerialClock
     56	 * third line: SerialData
     57	 *
     58	 * SYMMETRICAL APPROACH:
     59	 *   _______________________          LEFT
     60	 * _|         RIGHT         |______________________|
     61	 *     _   _         _   _   _   _         _   _
     62	 *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
     63	 *     _   _         _   _   _   _         _   _
     64	 *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
     65	 *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
     66	 *
     67	 * ACCURATE CLOCK APPROACH:
     68	 *   ______________          LEFT
     69	 * _|     RIGHT    |_______________________________|
     70	 *     _         _   _         _   _   _   _   _   _
     71	 *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
     72	 *     _         _   _          _      dummy cycles
     73	 *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
     74	 *    \_/       \_/ \_/        \_/
     75	 *
     76	 */
     77	bool i2s_accurate_sck;
     78
     79	/* McASP specific fields */
     80	int tdm_slots;
     81	u8 op_mode;
     82	u8 dismod;
     83	u8 num_serializer;
     84	u8 *serial_dir;
     85	u8 version;
     86	u8 txnumevt;
     87	u8 rxnumevt;
     88	int tx_dma_channel;
     89	int rx_dma_channel;
     90};
     91/* TODO: Fix arch/arm/mach-davinci/ users and remove this define */
     92#define snd_platform_data davinci_mcasp_pdata
     93
     94enum {
     95	MCASP_VERSION_1 = 0,	/* DM646x */
     96	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
     97	MCASP_VERSION_3,        /* TI81xx/AM33xx */
     98	MCASP_VERSION_4,	/* DRA7xxx */
     99	MCASP_VERSION_OMAP,	/* OMAP4/5 */
    100};
    101
    102enum mcbsp_clk_input_pin {
    103	MCBSP_CLKR = 0,		/* as in DM365 */
    104	MCBSP_CLKS,
    105};
    106
    107#define INACTIVE_MODE	0
    108#define TX_MODE		1
    109#define RX_MODE		2
    110
    111#define DAVINCI_MCASP_IIS_MODE	0
    112#define DAVINCI_MCASP_DIT_MODE	1
    113
    114#endif